Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-03-19
2004-09-14
Gurley, Lynne (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S634000, C438S637000, C438S638000, C438S700000, C438S707000, C438S708000, C438S710000, C438S717000, C438S725000, C438S736000, C438S737000, C438S738000
Reexamination Certificate
active
06790766
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more specifically, it relates to a method of fabricating a semiconductor device including a low dielectric constant insulator film.
2. Description of the Background Art
The importance of a copper wiring technique has recently been increased following requirement for a high-speed semiconductor integrate circuit. In this regard, there is proposed a dual damascene structure obtained by combining a copper wire and a low dielectric constant interlayer dielectric film with each other. The dual damascene structure is generally constructed by forming a wiring trench and a contact hole (via hole) in an insulator film by etching, filling up the wiring trench and the contact hole with a metal and thereafter removing an excess depositional portion by polishing thereby forming a buried wire.
FIGS. 21
to
23
are sectional views for illustrating a conventional process of fabricating a semiconductor device including a dual damascene structure. The conventional process of fabricating a semiconductor device including a dual damascene structure is now described with reference to
FIGS. 21
to
23
.
First, a first low dielectric constant interlayer dielectric film
102
consisting of an organic polymer is formed on a metal cap barrier film
101
, as shown in FIG.
21
. An etching stopper film
103
consisting of SiO
2
or Si
3
N
4
having an opening
103
a
is formed on a prescribed region of the first low dielectric constant interlayer dielectric film
102
. A second low dielectric constant interlayer dielectric film
104
consisting of an organic polymer is formed to cover the etching stopper film
103
. Thereafter a hard mask
105
consisting of an SiO
2
or Si
3
N
4
film having an opening
105
a
is formed on the second low dielectric constant interlayer dielectric film
104
.
As shown in
FIG. 22
, the hard mask
105
and the etching stopper film
103
are employed as masks for plasma-etching the second and first low dielectric constant interlayer dielectric films
104
and
102
, thereby simultaneously forming a wiring trench
107
and a via hole (contact hole)
106
.
As shown in
FIG. 23
, the via hole
106
and the wiring trench
107
are filled up with copper and an excess depositional portion is removed by polishing, thereby forming a buried wire
108
consisting of copper. Thus, the conventional semiconductor device including a dual damascene structure is formed.
In the aforementioned conventional method of fabricating a semiconductor device including a dual damascene structure, however, the etching stopper film
103
must be prepared from a material having a high etching selectivity with respect to the first and second low dielectric constant interlayer dielectric films
102
and
104
in the plasma etching step shown in FIG.
22
. In general, therefore, the etching stopper film
103
is formed by an SiO
2
film (dielectric constant: 3.9 to 4.5) or an Si
3
N
4
film (dielectric constant: 6 to 9) having a relatively high dielectric constant. In order to prevent the via hole
106
from deforming in this case, the thickness of the etching stopper film
103
consisting of SiO
2
or the like must be increased. In the final dual damascene structure shown in
FIG. 23
, therefore, the effective dielectric constant of the overall insulator film including the first low dielectric constant interlayer dielectric film
102
, the etching stopper film
103
and the second low dielectric constant interlayer dielectric film
102
is disadvantageously increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of fabricating a semiconductor device capable of increasing the etching selectivity of a low dielectric constant insulator film without increasing the thickness of the etching mask layer to an etching mask layer such as an etching stopper film.
Another object of the present invention is to suppress increase of the effective dielectric constant of the overall insulator film including the etching mask layer and the low dielectric constant insulator film in the aforementioned method of fabricating a semiconductor device.
In order to attain the aforementioned objects, a method of fabricating a semiconductor device according to a first aspect of the present invention comprises steps of forming a first insulator film including a polymer film containing C and H, forming a first etching mask layer containing Si on a prescribed region of the first insulator film, and plasma-etching the first insulator film through a mask of the first etching mask layer with plasmas of etching gases containing a nitrogen atom and monochromated ions energy having a narrow energy width.
When plasma-etching the first insulator film with the etching gas containing a nitrogen atom and the ions having a narrow energy width through the mask of the first etching mask layer containing an Si atom (silicon atom) thereby adjusting the range of the monochromatic ion energy in the method of fabricating a semiconductor device according to the first aspect, the etching selectivity of the first insulator film such as a low dielectric constant insulator film to the first etching mask layer can be easily increased. Thus, the thickness of the first etching mask layer consisting of a material having a relatively high dielectric constant may not be increased, whereby the overall insulator film including the first insulator film and the first etching mask layer can be inhibited from increase of the effective dielectric constant.
In the aforementioned method of fabricating a semiconductor device according to the first aspect, the plasma etching step preferably includes a step of plasma-etching the first insulator film with the etching gas including either ammonia gas or mixed gas of nitrogen gas and hydrogen gas and the monochromated ion energy of at least 200 eV and not more than 600 eV. According to this structure, the etching selectivity of the first insulator film such as a low dielectric constant insulator film to the first etching mask layer can be increased to at least about 5.
In this case, the plasma etching step preferably includes a step of plasma-etching the first insulator film with the etching gas including either ammonia gas or mixed gas of nitrogen gas and hydrogen gas and the monochromatic ion energy of at least 400 eV and not more than 600 eV. According to this structure, the etching selectivity of the first insulator film such as a low dielectric constant insulator film to the first etching mask layer can be increased to at least about 5 and the etching rate can be increased.
In the aforementioned method of fabricating a semiconductor device according to the first aspect, the plasma etching step preferably includes a step of plasma-etching the first insulator film with the etching gas including nitrogen gas and the monochromatic ion energy of at least 200 eV and not more than 400 eV. According to this structure, the etching selectivity of the first insulator film such as a low dielectric constant insulator film to the first etching mask layer can be increased to at least about 5.
In the aforementioned method of fabricating a semiconductor device according to the first aspect, the first etching mask layer is preferably a film containing an Si atom. When the first etching mask layer contains an Si atom, the etching selectivity of the first insulator film such as a low dielectric constant insulator film to the first etching mask layer can be increased by employing the aforementioned etching conditions. In this case, the first etching mask layer preferably includes at least one film selected from a group of an Si
3
N
4
film, an SiO
2
film and an SiOCH film.
In the aforementioned method of fabricating a semiconductor device according to the first aspect, the first etching mask layer preferably includes an Si
3
N
4
film, and the plasma etching step preferably includes a step of plasma-etching the first insulator film with the etching gas including ammonia g
Nakamura Moritaka
Yamaoka Yoshikazu
Gurley Lynne
McDermott Will & Emery LLP
Sanyo Electric Co,. Ltd.
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