Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2005-06-07
2005-06-07
Zarneke, David A. (Department: 2829)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S522000, C438S519000
Reexamination Certificate
active
06902992
ABSTRACT:
Provided is a semiconductor device having a semiconductor resistance element, which is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration difficult to be controlled, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a doner concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.
REFERENCES:
patent: 4228450 (1980-10-01), Anantha et al.
patent: 4298401 (1981-11-01), Nuez et al.
patent: 3-53-126875 (1978-11-01), None
patent: 3-54-056777 (1979-05-01), None
patent: 3-57-018354 (1982-01-01), None
patent: 3-61-002361 (1986-01-01), None
patent: 3-62-060252 (1987-03-01), None
patent: 3-62-143478 (1987-06-01), None
patent: 4-01-268049 (1989-10-01), None
patent: 4-03-169063 (1991-07-01), None
patent: 4-04-067666 (1992-03-01), None
patent: 4-05-114699 (1993-05-01), None
patent: 4-05-315547 (1993-11-01), None
Goto et al., “Two Dimensional Numerical Simulation of Side-Gating Effect in GaAs MESFET's,” IEEE, 1990, pp. 1821-1827, vol. 37.
Sonnenschein Nath & Rosenthal LLP
Sony Corporation
Zarneke David A.
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