Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-14
2002-04-30
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S633000, C438S637000, C438S672000, C257S760000, C257S774000
Reexamination Certificate
active
06380071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and more particularly, to a method of fabricating a semiconductor device that makes it possible to form via holes or contact holes in an interlevel dielectric layer in self-alignment with corresponding conductors.
2. Description of the Related Art
Recently, the integration level of Large-Scale Integrated Circuits (LSIs) has been increasing and as a result, there has been the strong need to decrease not only the size of electronic elements such as transistors to be integrated on a semiconductor substrate but also the pitch of conductive lines in each wiring layer. Thus, on designing the layout of via holes or contact holes, which are used for electrically interconnecting the conductive lines in a wiring layer with the conductive lines in an overlying wiring layer, the alignment margin of the via or contact holes has become necessary to be determined to be equal to or less than the alignment accuracy of a specific LSI fabrication system.
For example, the layout of a square via hole
152
and a conductive line
151
as shown in
FIG. 1
is considered. In this case, the via hole
152
is located to entirely overlap with the vicinity of an end of the conductive line
151
in such a way that two widthwise edges
151
a
and
151
b
of the line
151
are respectively apart from corresponding or opposing edges
152
a
and
152
b
of the hole
152
at equal distances (i.e., an alignment margin) M. If the LSI fabrication system to be used has an alignment accuracy A, the alignment margin M needs to be adjusted to be equal to or less than the accuracy A, i.e., M≦A.
In the explanation presented below, the term “via hole” means not only a via hole but a contact hole.
If the margin M is set to be equal to or less than the accuracy A, however, part of the hole
152
tends to deviate from the line
151
due to accumulation of alignment errors in the actual fabrication processes. This is explained in detail below with reference to FIG.
2
.
In
FIG. 2
, a thin dielectric layer
161
a
is formed on the surface of a semiconductor substrate
161
and then, the conductive line
151
is formed on the layer
161
a
. A thick interlayer dielectric layer
162
is formed on the layer
161
a to cover the line
151
. The layer
162
has the via hole
152
that penetrates vertically the layer
162
to the line
151
. Needless to say, the layout design is conducted in such a way that the hole
152
is located at the widthwise center of the line
151
, as shown in FIG.
1
. However, actually, the hole
152
is largely deviated from the desired or designed position due to accumulation of alignment or overlying errors among patterned masks, resulting in deviation of part of the hole
152
from the line
151
, as shown in FIG.
2
. In this state, as seen from
FIG. 2
, the upper corner and the side face of the line
151
and the dielectric layer
161
a
are exposed to the hole
152
.
Typically, the via hole
152
is formed by selectively removing the interlayer dielectric layer
162
using a patterned resist film (not shown) in a dry etching process. Thus, if the hole
152
is deviated from the desired position, as shown in
FIG. 2
, not only the top surface of the line
151
but also the upper corner and side face thereof are contacted with the etching gas in the dry etching process of the layer
162
for forming the hole
152
. This means that the line
151
is excessively etched in the dry etching process compared with the calculated etching amount of the line
151
, thereby producing a lot of etch residues that are unable or difficult to be entirely removed. As a consequence, there arises a problem that the yield of the etching process for forming the via hole
152
is lowered. Also, since the upper corner of the line
151
is waned or cut during the etching process, there arises another problem that the electrical resistance of the resultant line
151
is higher than the desired value.
To avoid these problems, conventionally, various methods of forming the via hole
152
in self-alignment to the conductive line
151
have been developed and disclosed. One of the methods is explained below with reference to
FIGS. 3A
to
3
D, which is disclosed in the Japanese Non-Examined Patent Publication No. 8-153796 published in June 1996.
First, as shown in
FIG. 3A
, a thin dielectric layer
121
a
is formed on the surface of a semiconductor substrate
121
that contains necessary electronic elements such as transistors therein. Next, a conductive layer (not shown) and a silicon dioxide (SiO
2
) layer (not shown) are successively formed on the layer
121
a
. These two layers are then patterned using the same resist mask, forming a conductive line
122
and a SiO
2
protection layer
123
located on the line
122
. The line
122
and the layer
123
constitute a lower wiring structure
130
. The state at this stage is shown in FIG.
3
A.
Subsequently, a silicon oxynitride (SiON) layer (not shown) is formed on the dielectric layer
121
a
over the whole substrate
121
and is etched back, forming a pair of SiON sidewalls
124
a
and
124
b
on the layer
121
a
at each side of the lower wiring structure
130
, as shown in FIG.
3
B.
A thick SiO
2
layer
125
is formed on the dielectric layer
121
a
over the whole substrate
121
as an interlayer dielectric layer, as shown in FIG.
3
C. The surface of the layer
125
is planarized and then, selectively removed in a dry etching process using a resist mask, thereby forming a via hole
127
to penetrate the layer
125
at a specific location. Since the SiO
2
protection layer
123
of the wiring structure
130
is removed in this dry etching process, the top surface of the conductive line
122
is exposed within the hole
127
. The state at this stage is shown in FIG.
3
C.
The etch rate of SiON is sufficiently lower than that of SiO
2
in the dry etching process for the SiO
2
interlayer dielectric layer
125
and therefore, the SiON sidewalls
124
a
and
124
b
are left substantially unetched. Thus, even if the via hole
127
is laterally shifted from its desired position along the surface of the substrate
121
and part of the hole
127
deviates from the conductive line
122
due to accumulation of alignment errors among patterned masks in the actual fabrication processes, the upper corner and the side face of the line
122
is protected by the sidewalls
124
a
and
124
b
not to be contacted with the etching gas. As a result, the above-described two problems that the yield of the etching process for forming the via hole
127
is lowered and that the electrical resistance of the resultant line
122
is higher than the desired value can be avoided.
Thereafter, as shown in
FIG. 3D
, the via hole
127
of the interlayer dielectric layer
125
is filled with a tungsten (W) plug
123
by a known method. An upperwiring structure
131
with a specific pattern is formed on the layer
125
. The plug
123
is contacted with a conductive line
126
of the structure
131
. In this way, the conductive line
126
of the upper wiring structure
131
is electrically connected to the conductive line
122
of the lower wiring structure
130
.
The prior-art method of fabricating a semiconductor device as shown in
FIGS. 3A
to
3
D solves theoretically the above-described two problems. However, it does not always solve the problems in the actual fabrication processes. Specifically, in the etching process for forming the conductive line
122
and the SiO
2
protection layer
123
of the lower wiring structure
130
, the structure
130
does not have the vertical side faces shown in
FIG. 3A
but the tilted side faces shown in FIG.
4
A. In other words, the structure
130
has a tapered cross section, not a straight cross section. (To facilitate understanding, the tapered shape is illustrated in
FIG. 4A
exaggeratingly.)
When the SiON layer
124
covering the whole substrate
121
is etched back, the layer
124
is subjected to the etching action o
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