Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

1999-05-21

2001-02-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S682000, C257S382000

Reexamination Certificate

active

06194298

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88106211, filed Apr. 19, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a self-aligned silicide layer.
2. Description of the Related Art
In a deep sub-micron semiconductor fabrication process, linewidth, contact area, and junction depth are greatly reduced. In order to effectively enhance the performance of devices, reduce device resistance, and reduce device resistancecapacitance (RC) delay, silicide layers has been used to form on a gate or a source/drain region in the fabrication process.
A process that is commonly used nowadays for forming a silicide layer in integration circuits is the self-aligned silicide (salicide) process.
FIGS. 1A through 1C
are schematic, cross-sectional views of a conventional self-aligned silicide process.
In
FIG. 1A
, an isolation structure
101
is formed in a substrate
100
. A gate
105
comprising a gate conductive layer
102
and a gate oxide layer
103
is formed on the substrate
100
. A spacer
104
is formed on the sidewall of the gate
105
. A source/drain region
112
is formed on opposite sides of the gate
105
in the substrate
100
. A pre-amorphous implantation (PAI) step is performed on the substrate
100
. The surfaces of the gate
105
and the source/drain region
112
are thus amorphized. In
FIG. 2B
, a metallic layer
122
is formed over the substrate
100
. Referring to
FIG. 1C
, an annealing step is performed. The metallic layer
122
on the gate
105
and the source/drain region
112
is converted into silicide layers
124
and
126
. The metallic layer
122
, which does not react, is removed by selective wet etching. The silicide layer
124
is formed on the gate
105
and the silicide layer
126
is formed on the source/drain region
112
. Since there is no patterning step, such as a photolithography step, required for forming the silicide layers
124
and
126
, the above-described process is called a self-aligned silicide process.
The conventional method amorphizes the substrate
100
and the gate
105
by ion implantation (shown in FIG.
1
), which implants ions directly into the substrate
100
. Because there is no buffer layer covering on the substrate
100
, the ions easily penetrate into deep-inner portion of the substrate
100
and cause a channel effect to occur. This further affects properties of devices.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a semiconductor device. A conductive layer is formed on a substrate. A spacer is formed on a sidewall of the conductive layer. A thin metallic layer is formed over the substrate. An ion implantation step is performed. A first seeding layer is formed between the first metallic layer and the conductive layer. A second seeding layer is formed between the first metallic layer and the substrate. A second metallic layer is formed over the substrate. An annealing step is performed to form a self-aligned silicide layer on the conductive layer. The first metallic layer and the second metallic layer that do not react are removed.
The present invention first forms the thin metallic layer over the substrate and then performs the ion implantation step with the thin metallic layer serving as a mask. Thus, the present invention prevents occurrence of the channel effect and maintains electrical properties of devices. The reliability of the devices is further increased. In addition, the invention forms the first and the second seeding layers on the gate conductive layer and the source/drain region, so that the formation of self-aligned silicide layers is hastened.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5635746 (1997-06-01), Kirmura et al.
patent: 5902121 (1999-05-01), Goto
patent: 5956617 (1999-09-01), Kirmura et al.
patent: 6066532 (2000-05-01), Chen et al.

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