Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

1999-08-12

2001-11-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S199000, C438S218000

Reexamination Certificate

active

06319803

ABSTRACT:

This application claims the benefit of Korean Application No. 1910/1999 filed Jan. 22, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of fabricating a semiconductor device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for fabricating a semiconductor device having a local interconnection (LI) between a gate and a junction.
2. Discussion of the Related Art
FIGS. 1A
to
1
C are cross-sectional views illustrating the process steps of fabricating a semiconductor device according to a related background art.
Initially referring to
FIG. 1A
, a P well
21
and an N well
22
which have a predetermined depth are formed in a semiconductor substrate
11
. A thin silicon oxide (SiO
2
) layer is formed on the exposed surface of the semiconductor substrate
11
which has an isolation layer
13
selectively formed to define an active region. A thick polysilicon layer is then deposited on the thin silicon oxide layer as well as on the isolation layer
13
. Using a photolithographic process, a photoresist film (not shown) is formed on the polysilicon layer formed at a gate region. In this process, the photoresist film acts as a mask, and a portion of the polysilicon layer is removed by a plasma etching method. Thus, first, second, third, and fourth gates
37
a
,
37
b
,
37
c
, and
37
d
are formed on the semiconductor substrate
11
, and only portions
23
a
and
23
b
of the silicon oxide layer remain below the first and second gates
37
a
and
37
b
. After the first to fourth gates
37
a
to
37
d
are formed, the photoresist film is removed from each gate.
Thereafter, using photolithography, the N well region
22
is covered with a photoresist film (not shown) while the P well region
21
is exposed. The first gate
37
a
is used as a mask, so that a self-alignment process is used in executing an ion implantation to form a lightly doped drain (LDD) region in the semiconductor substrate of the P well region
21
. Thus, a lightly doped N-type region
40
is formed at both sides of the first gate
37
a
in the semiconductor substrate.
Similarly, after removing the photoresist film, only the N well region
22
is exposed by photolithographic process. The second gate
37
b
is then used as a mask to form a lightly doped P-type region
41
of the N well region
22
by an ion implantation. Thus, the lightly doped P-type region
41
is formed at both sides of the second gate
37
b
in the semiconductor substrate by a self-alignment process.
The isolation layer
13
is formed of a silicon oxide (SiO
2
) layer formed by a shallow trench isolation (STI) method. The above-mentioned thin silicon oxide film is grown on the semiconductor substrate
11
by thermal oxidation. The first, second, third, and fourth gates
37
a
,
37
b
,
37
c
, and
37
d
are polysilicon layers having a thickness of in the range of 2500 to 4000 Å. Also, the polysilicon layers have a fine grain structure and are deposited by chemical vapor deposition (CVD).
The first and second gates
37
a
and
37
b
protect the respective the silicon oxide (SiO
2
) layers
23
a
and
23
b
from a channeling effect during the subsequent ion implantation. The photoresist film is removed using a solvent or oxygen plasma.
In the process of forming the lightly doped N-type region
40
, ion implantation is performed with phosphorus (P) ions of 1.0×10
13
to 1.0×10
14
atoms/cm
2
using an acceleration energy of 40 KeV. Simultaneously, the first and third gates
37
a
and
37
c
are also lightly doped by ion implantation. In forming the lightly doped P-type region
41
, (using BF
2
as a boron source) ion implantation is performed with boron ions of 1.0×10
13
to 1.0×10
14
atoms/cm
2
using an acceleration energy of 50 KeV. Similarly, the second and fourth gates
37
b
and
37
d
are lightly doped by ion implantation.
Referring to
FIG. 1B
, a silicon oxide (SiO
2
) layer is deposited on the entire surface of the semiconductor substrate
11
by CVD. Then, silicon oxide layer is etched by anisotropic plasma etching to form a plurality of spacers
43
on sides of the gates
37
a
,
37
b
,
37
c
, and
37
d.
Subsequently, a photolithography is performed to cover the N well region
22
with a photoresist film (not shown) and to expose the P well region
21
. The first gate
37
a
is used as a mask in performing an N-type ion implantation in the semiconductor substrate of the P well region
21
. Thus, a self-alignment process is used in forming a heavily doped N-type region
45
. Similarly, a heavily doped P-type region
47
is formed by using the second gate
37
b
as a mask for performing a P-type ion implantation. In this process, the photoresist film (not shown) covers only the P well region
21
, so that the N well region
22
is exposed for the process.
Thereafter, the semiconductor substrate
11
is subjected by annealing at the temperature in the range of 900 to 950° C. to form source regions
41
and
47
of PMOS and drain regions
40
and
45
of NMOS, which have predetermined junction depths.
In forming the spacers
43
, the silicon oxide layer formed by a CVD method is etched by an anisotropic plasma etching process using a gas such as He, C
2
H
6
and CHF
3
.
In the step of forming the heavily doped N-type region
45
, ion implantation is performed with As ions of 5.0×10
15
atoms/cm
2
using an acceleration energy of 100 KeV. At the same time, the first and third gates
37
a
and
37
c
are heavily doped by ion implantation. Similarly, the heavily doped P-type region
47
is formed by ion-implanting boron ions of 3.0×10
15
atoms/cm
2
using an acceleration energy of 50 KeV. Simultaneously, the second and fourth gates
37
b
and
37
d
are heavily doped by ion implantation.
AS shown in
FIG. 1C
, CoSi
2
layers
49
a
and
49
b
are formed on the source and drain regions
47
and
45
and on the upper surface of the first, second, third, and fourth gates
37
a
,
37
b
,
37
c
, and
37
d
by high temperature sputtering and in-situ vacuum annealing methods. Then, a thin silicon nitride (Si
3
N
4
) layer (not shown) and a thick borophosphosilicate glass (BPSG) layer
51
are deposited on the entire surface of the semiconductor substrate
11
by CVD. The BPSG layer is removed to have a predetermined thickness by chemical-mechanical polishing (CMP), so that the surface of the BPSG layer
51
is planarized. Using a photoresist film (not shown) as a mask, a predetermine portion where photoresist film is not covered is removed by plasma etching. Thus, this process removes a portion of the CoSi
2
layer
49
a
on the source and drain regions
47
and
45
and a portion of the spacers
43
, and the isolation layer
13
of the third and fourth gates
37
c
and
37
d
. The photoresist film is then removed from the gates.
A thin titanium (Ti)/titanium nitride (TiN) film (not shown) and a thick tungsten (W) layer
53
are deposited on the entire surface of the semiconductor substrate
11
by a sputtering method. A portion of the multi-layers (W/TiN/Ti) deposited on the BPSG layer are removed completely by a CMP method. Thus, a portion of the layers (W/TiN/Ti) remain only in a predetermined groove-type portion. As a result, the layers
53
acts as a local interconnection (LI) between the gate and junction.
In the above-described process, the CoSi
2
layer is formed of a 150 Å thick salicide layer which is converted from a cobalt film deposited by a sputtering method in a salicide process. The silicon nitride layer Si
3
N
4
is deposited to have a thickness in the range of 500 to 1000 Å by CVD. The BPSG layer is deposited to have a thickness of 8000 to 10000 Å using CVD. The Ti layer is formed to have a thickness in the range of 200 to 400 Å by sputtering. The W layer is deposited to have a thickness of 4000 to 5500 Å by sputtering.
However, the above-described related back

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