Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

1993-10-15

2001-06-12

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S247000, C438S390000, C438S433000

Reissue Patent

active

RE037228

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming trench isolation between elements in a semiconductor device without humps in subthreshold current regions.
Many non LOCOS isolation techniques have been reported to realize submicron isolation in a semiconductor device (T. Shibata et al., IEDM Tech. Dig., pp. 27-30, Dec. 1983; K. Terada et al., IEEE Trans. on Electron Devices, Vol. ED-31, pp. 1308-1313, Sept. 1981). Above all, the trench isolation technique with buried oxide is thought of as a leading technique. However, n-MOS FETs fabricated with the trench isolation frequently show humps in subthreshold current regions and a reverse narrow width effect in threshold voltages (T. Iizuka et al., IEDM Tech. Dig., pp. 380-383, Dec. 1981). In order to eliminate these disadvantages, increasing boron concentration at side-walls of channel edges seems to be effective. For implanting boron ions into the side-walls, tapered etching of the isolation side-walls in a silicon substrate was proposed (Kurosawa et al., IEDM Tech. Dig., pp. 384 Dec. 1981). That is, V-letter-shaped isolation is used to increase boron concentration at side-walls thereof. However, the minimum isolation width W
I
may be limited by 2D tan &agr;, where D and &agr; are isolation depth and taper angle, respectively. For example, W
I
is limited to be about 0.69 &mgr;m for D=0.6 &mgr;m and &agr;=60°.
SUMMARY OF THE INVENTION
The present invention, therefore, has as its principal object the provision of an improved method of forming trench isolation for a semiconductor device in which vertical side-walls are used instead of tapered side-walls and which can suppress the hump currents and control the narrow width effect.
Another object of the invention is to provide an improved method of forming trench isolation for a semiconductor device which may be applicable to submicron isolation width of below 0.5 &mgr;m.
These and other objects are accomplished by a method of fabricating a semiconductor device which comprises a step of forming a trench selectively on a semiconductor substrate, a step of positioning said semiconductor substrate in a first position inclined to a plane vertical to ion beams, a step of implanting ions by emitting ion beams to a side-wall of the trench of the semiconductor substrate at the first position, a step of positioning said semiconductor substrate in a second position which is different from said first position by rotating it, and a step of injecting ions by emitting ion beams to a side-wall of the trench of the semiconductor substrate at the second position.
In an illustrated embodiment, ions to be implanted are boron. In ion implantation of n times, the angle of rotation of the semiconductor substrate of each time is substantially an integer multiple of 360°
. The trench possesses four vertical side-walls which substantially contact with each other at 90°, and a bottom which contacts with each side-wall substantially at 90°. Ions are implanted into the bottom of trench by emitting ion beams in the direction perpendicular to the surface of the semiconductor substrate. The side-walls are implanted by orienting a normal of a plane containing the surface of the semiconductor at an angle of inclination of substantially 8° to the direction of the implanting ions. The semiconductor substrate is a semiconductor wafer.
This invention also relates to a method of fabricating a semiconductor device which comprises a step of forming a trench having four vertical side-walls contacting at 90° and a bottom selectively on a semiconductor substrate, a step of positioning the semiconductor substrate while emitting ion beams onto a first side-wall of said semiconductor substrate from a direction inclined to the normal of a plane which contains the principal surface of said semiconductor substrate, a step of implanting ions into said first side-wall by emitting ion beams onto said side-wall, a step of, positioning the semiconductor substrate while emitting said ion beams onto a second side-wall which adjoins said first side-wall by rotating said semiconductor substrate by 90°, a step of implanting ions into said second side-wall by emitting ion beams onto said second side-wall, a step of positioning the semiconductor substrate while emitting said ion beams onto a third side-wall which adjoins said second side-wall by rotating said semiconductor substrate by 90°, a step of implanting ions into said third side-wall by emitting ion beams onto said third side-wall, a step of positioning the semiconductor substrate while emitting said ion beams onto a fourth side-wall which adjoins said third side-wall by rotating said semiconductor substrate by 90°, and a step of implanting ions onto said fourth side-wall by emitting ion beams onto said fourth side-wall.
This invention further relates to a method of fabricating a semiconductor device which comprises a step of forming a trench on a semiconductor substrate, a step of emitting ion beams to the principal plane of said semiconductor substrate from an oblique direction, a step of changing the relative positions of ion beams and semiconductor substrate after a first ion beam irradiation, and a step of emitting ion beams a second time after changing position, whereby ions are implanted into the side-walls of the trench.
According to the present invention as described herein, the following benefits, among others, are obtained:
(1) Ions can be easily implanted into untapered vertical side-walls and generation of hump currents can be prevented, so that a semiconductor device of high density and excellent properties can be provided.
(2) Besides, since a submicron isolation width below 0.5 &mgr;m can be achieved, a semiconductor device of high precision can be manufactured.
While the novel features of the invention are set forth with particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawing, in which:


REFERENCES:
patent: 4653177 (1987-03-01), Lebowitz et al.
patent: 4756793 (1988-07-01), Peek
patent: 63-227017 (1988-09-01), None
Nakamura et al., “Buried Isolation Capacitor (BIC) Cell for Megabit Mos Dynamic RAM,” IERDM 1984, pp 236-239.*
Nikkei Microdevices, No. 8, 1994, pp 38-39.*
Fuse et al., “Indirect Trench Sidewal Doping by Implantion of Reflected Ions”, Applied Physics Letters, Apr. 17, 1989. pp 1534-1536.

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