Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1996-10-22
2000-04-18
Nelms, David
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438633, 438637, 438645, 438692, 438778, H01L 2176
Patent
active
060514779
ABSTRACT:
A method of fabricating a SOI wafer is disclosed, which comprises the steps of: providing a silicon-on-insulator wafer wherein an oxide is formed between a base substrate and a devise substrate; thinning the device substrate to form a Si layer; etching the Si layer to expose the surface of the oxide film, to form trenches; forming polishing stoppers within the trenches, each polishing stopper have a smaller thickness in its center portion and a greater thickness in its outer portion; heat-treating the polishing stopper; and polishing, via chemical and mechanical polishing, the Si layer using the polishing stopper to form a device formation layer.
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English translation of Abstract for JP 04-67634 (Mar. 3, 1992).
Berry Renee R.
Hyundai Electronics Industries Co,. Ltd.
Nelms David
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