Method of fabricating semiconductor device

Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S519000, C438S527000, C438S039000, C438S039000

Reexamination Certificate

active

07118983

ABSTRACT:
An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p
junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p
junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and′ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide12, so that the source/drain region (S and D) can have a low resistance, and a p
junction leakage can be reduced.

REFERENCES:
patent: 5027185 (1991-06-01), Liauh
patent: 5273914 (1993-12-01), Miyajima et al.
patent: 5314832 (1994-05-01), Deleonibus
patent: 5389809 (1995-02-01), Haken et al.
patent: 5563100 (1996-10-01), Matsubara
patent: 5583067 (1996-12-01), Sanchez
patent: 5728625 (1998-03-01), Tung
patent: 5780349 (1998-07-01), Naem
patent: 5818092 (1998-10-01), Bai et al.
patent: 5888888 (1999-03-01), Talwar et al.
patent: 5899720 (1999-05-01), Mikagi
patent: 6-84824 (1994-03-01), None
patent: 7-115196 (1995-05-01), None
patent: 07-115196 (1995-05-01), None
patent: 818085 (1996-07-01), None
patent: 8274047 (1996-10-01), None
patent: 9-121050 (1997-05-01), None
patent: 9-219516 (1997-08-01), None
patent: 9-251967 (1997-09-01), None
C.-P. Chao, et al., “Low Resistance Ti or Co SalicidedRaised Source/Drain Transistors for Sub-0.13 μm CMOS Technologies”, Technical Digest International Electron Device meeting, Dec. 7-10, 1997, IEEE, pp. 5.2.1-5.2.4.
Electrochemical Society Active Member, vol. 134, No. 4, pp. 925-935.
IEDM 95, pp. 449-452.
Korean Office Action dated Jun. 20, 2005, for Korean App. No. 2000-7002649 (and English translation of Reasons of Rejection thereof).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating semiconductor device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3676001

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.