Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-09-25
2000-10-24
Thomas, Tom
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438597, 438648, 438649, 438651, 438655, 438656, 438663, 438664, 438682, 438683, 438685, 257368, 257382, 257383, 257384, 257389, 257390, H01L 213205, H01L 21324, H01L 2144, H01L 214763
Patent
active
061366773
ABSTRACT:
A method of fabricating a semiconductor device includes the steps of providing a semiconductor chip (10) with a memory area (22) and a logic area (26). The memory area (22) and the logic area (26) each have gate structures (50) formed therein. The step of sequentially forming silicided junctions (44) in the logic area (26) and implanted junctions in the memory area (26) is also included.
REFERENCES:
patent: 4145803 (1979-03-01), Tasch, Jr.
patent: 4443930 (1984-04-01), Hwang et al.
patent: 4561170 (1985-12-01), Doering et al.
patent: 4814854 (1989-03-01), Tigelaar et al.
patent: 4868133 (1989-09-01), Huber
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5060195 (1991-10-01), Gill et al.
patent: 5394002 (1995-02-01), Peterson
patent: 5425392 (1995-06-01), Thakur et al.
patent: 5453389 (1995-09-01), Strain et al.
patent: 5455205 (1995-10-01), Umimoto et al.
patent: 5459353 (1995-10-01), Kanazawa
patent: 5462898 (1995-10-01), Chen et al.
patent: 5472887 (1995-12-01), Hutter et al.
patent: 5514908 (1996-05-01), Liao et al.
patent: 5536676 (1996-07-01), Cheng et al.
patent: 5550090 (1996-08-01), Ristic et al.
patent: 5571744 (1996-11-01), Demirlioglu et al.
patent: 5584964 (1996-12-01), Umimoto et al.
patent: 5597756 (1997-01-01), Fazan et al.
patent: 5600598 (1997-02-01), Skjaveland et al.
patent: 5605854 (1997-02-01), Yoo
patent: 5606189 (1997-02-01), Adan
patent: 5622882 (1997-04-01), Yee
patent: 5624867 (1997-04-01), Cheng et al.
patent: 5710438 (1998-01-01), Oda et al.
patent: 5851921 (1998-12-01), Gardner et al.
patent: 5899735 (1999-05-01), Tseng
Patent Abstract of Japan, Publication No. 05190811, dated Jul. 30, 1993.
Patent Abstract of Japan, Publication No. 05190809, dated Jul. 30, 1993.
Braden Stanton C.
Siemens Aktiengesellschaft
Souw Bernard E.
Thomas Tom
LandOfFree
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