Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-04-18
2001-07-03
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S399000, C438S253000, C438S256000
Reexamination Certificate
active
06255187
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 99-14272, filed on Apr. 21, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor memory device. More particularly, the present invention relates to a method of fabricating a stacked capacitor using electroplating.
As the integration of dynamic random access memories (DRAMs) has increased, methods have been proposed for thinning a dielectric film of a capacitor to increase capacitance within a limited cell area, or for changing the structure of a capacitor lower electrode to a three-dimensional structure to increase the effective area of a capacitor.
However, even though these methods have been adopted, it is difficult to obtain a sufficient capacitance for device operation in 1-Gbit or greater DRAM memory devices using an existing dielectric. In order to solve the above problem, research has actively pursued methods for replacing the dielectric film of a capacitor with a thin film having a high dielectric constant, such as (Ba,Sr)TiO
3
(BST), PbZrTiO
3
(PZT), and (Pb,La)(Zr,Ti) (PLZT) films.
In conventional devices, when a high dielectric material such as BST is used in a DRAM, a buried contact (BC) is initially formed by a conductive plug such as doped polysilicon. An electrode material is then deposited to form a lower electrode, and the dielectric material is deposited, thereby fabricating the lower portion of a capacitor.
In the capacitor using the above-described high dielectric film such as a BST film, a platinum-group element or an oxide thereof, e.g., Pt, Ir, Ru, RuO
2
, or IrO
2
, is used as an electrode material. However, Pt, which has an excellent oxidation-resistant property, is greatly reactive with silicon. Hence, when the platinum-group elements, such as Pt, or their oxides are employed as an electrode material, a BC and a lower electrode will react with each other and mutually diffuse when the electrode material contacts the doped polysilicon that forms the BC.
Thus, in a conventional method of fabricating a capacitor, a barrier layer for separating the BC from the lower electrode must be formed between these two layers to prevent mutual reaction and diffusion from occurring between them.
However, when a barrier layer is formed between the BC and the lower electrode, oxygen may diffuse and enter into the sidewalls of the barrier layer during the formation of a dielectric layer. As a result, the conventional technique requires a special process for forming spacers to cover the sidewalls of a barrier layer, in order to prevent oxygen from diffusing through the sidewalls of a barrier layer. Consequently, the capacitor fabricating process is complicated.
Also, in the conventional technique, in order to form a lower electrode using a platinum-group metal as an electrode material, a conductive layer is formed of the platinum-group metal, and is then patterned by dry etching to form a storage node. However, the conductive layer formed of the platinum-group metal is very difficult to dry etch. As a result, when forming memory devices that have a storage node of 300 nm or less in width, particularly in 4-Gbit or more DRAMs, there is a limit in forming a lower electrode by dry etching.
SUMMARY OF THE INVENTION
To solve the above problems, an object of the present invention is to provide a method of fabricating a stacked capacitor without the need to form a barrier layer between a buried contact (BC) and a lower electrode.
Another object of the present invention is to provide a method of fabricating a stacked capacitor, by which dry etching of a conductive layer to separate storage nodes is not required when a lower electrode is formed of a conductive film such as a metal of the platinum group, and there are no misalignment problems between a BC and the lower electrode.
Accordingly, to achieve the above objects, the present invention provides a method of fabricating a stacked capacitor. In this method, a semiconductor substrate is prepared having exposed conductive areas. An interlayer insulative layer is formed over the semiconductor substrate, the interlayer insulative layer having buried contact holes that expose the conductive areas. A lower conductive seed layer is then formed over innerwalls of the buried contact holes and an upper surface of the interlayer insulative layer. Non-conductor patterns are formed over the lower conductive seed layer and the upper surface of the interlayer insulative layer, the non-conductor patterns having storage node holes that expose the buried contact holes. And then buried contacts that fill the buried contact holes, and lower electrodes that fill the storage node holes are simultaneously formed by a lower electroplating process.
The lower conductive seed layer preferably comprises a material selected from the group consisting of a platinum-group metal, a platinum-group metal oxide, a conductive perovskite material, a conductive metal, a metal silicide and a metal nitride, or a mixture of two or more of these materials. The lower conductive seed layer may also comprise a material selected from the group consisting of Pt, Rh, Ru, Ir, Os, Pd, PtO
X
, RhO
X
, RuO
X
, IrO
X
, OsO
X
, PdO
X
, CaRuO
3
, SrRuO
3
, BaRuO
3
, BaSrRuO
3
, CalrO
3
, SrIrO
3
, BaIrO
3
, (La,Sr)CoO
3
, Cu, Al, Ta, Mo, W, Au, Ag, WSi
x
, TiSi
x
, MoSi
x
, CoSi
x
, NiSi
x
, TaSi
x
, TiN, TaN, WN, TiSiN, TiAlN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, TaSiN, and TaAlN, or a mixture of two or more of these materials.
The non-conductor pattern preferably comprises a material selected from the group consisting of boro-phospho-silicate glass (BPSG), spin-on glass (SOG), phospho-silicate glass (PSG), a photoresist, SiO
X
, SiN
X
, SiON
X
, TiO
X
, AlO
X
, and AlN
X
, or a mixture of two or more materials.
The lower electroplating process is preferably performed using ammonium platinum nitrite (Pt(NH
3
)
2
(NO
2
)
2
), ammonium chloroplatinate ((NH
4
)
2
PtCl
6
), or chloroplatinic acid (H
2
PtCl
6
) as a plating solution. The lower electroplating process may also be performed using a plating solution in which metal salt containing a material selected from the group consisting of Pt, Ir, Ru, Rh, Os, Pd, Au, and Ag, or a mixture of two or more of these materials, is dissolved.
The method of fabricating a stacked capacitor may further comprise exposing a portion of the lower conductive seed layer over the upper surface of the interlayer insulative layer by removing the non-conductor patterns, after forming the buried contacts and the lower electrodes, and exposing the upper surface of the interlayer insulative layer by removing the exposed portion of the lower conductive seed layer. The exposed portion of the lower conductive seed layer is preferably removed by dry etching.
The method of fabricating a stacked capacitor may further comprise forming a dielectric layer over the lower electrode, after exposing the upper surface of the interlayer insulative layer, and forming an upper electrode over the dielectric layer.
The dielectric layer preferably comprises a material selected from the group consisting of Ta
2
O
5
, Al
2
O
3
, AlN, SrTiO
3
(STO), (Ba,Sr)TiO
3
(BST), PbZrTiO
3
(PZT), SrBi
2
Ta
2
O
9
(SBT), (Pb,La)(Zr,Ti)O
3
(PLZT), and Bi
4
Ti
3
O
12
, or a mixture of two or more of these materials.
The upper electrode is preferably formed by chemical vapor deposition (CVD), sputtering, or metal-organic deposition (MOD). The upper electrode is preferably formed of a material selected from the group consisting of a platinum-group metal, a platinum-group metal oxide, a conductive perovskite material, a conductive metal, a metal slicide, and a metal nitride, or a mixture of two or more of these materials.
The forming of the upper electrode may further comprise forming an upper conductive seed layer over the dielectric layer, and forming an upper electrode layer over the upper conductive seed layer by an upper electroplating process.
The upper conductive seed layer preferably
Dang Trung
Jones Volentine, L.L.C.
Samsung Electronics Co,. Ltd.
LandOfFree
Method of fabricating self-aligning stacked capacitor using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating self-aligning stacked capacitor using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating self-aligning stacked capacitor using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2505022