Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-04-05
2001-03-27
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S720000, C438S721000, C438S723000, C438S724000
Reexamination Certificate
active
06207579
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial. no. 88103043, filed Mar. 1, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a self-aligned storage node.
2. Description of the Related Art
Because the function of a microprocessor becomes more powerful and its software program becomes more complicated, there is a correspondingly greater need for a high-capacity DRAM. As the integration of the DRAM increases, a memory cell, which comprises a transfer field effect transistor (TFET) and a storage capacitor, is commonly used.
As the DRAM integration increases, the size of a DRAM capacitor must be decreased. In order to maintain the capacity of the capacitor, the surface area of the capacitor must be increased. Thus, a stacked capacitor has been developed.
According to the fabrication process, the stacked capacitors are separated into two types: capacitor over bit line (COB) and capacitor under bit line (CUB). As the DRAM integration increases, an overlay margin between the storage node contact of the COB and the bit line is reduced. In order to provide sufficient space for forming the storage node contact, the width between the storage node contact and the bit line must be decreased as much as possible. This, in turn, causes difficulties in fabricating bit lines and may also break the bit lines.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a self-aligned storage node. A first insulating layer is formed on a substrate. A preserve layer is formed on the first insulating layer. A bit line contact and a storage node contact are formed in the preserve layer and the first insulating layer. The bit line contact and the storage node contact are in contact with a source/drain region in the substrate. A second insulating layer is formed to cover the bit line contact, the storage node contact, and the preserve layer. A storage node plug and a cap layer are formed in a second insulating layer. The cap layer is formed on the storage node plug. The storage node plug connects to the storage node contact. The second insulating layer is patterned to form a first opening that exposes the bit line contact. In order to provide a good isolation between a bit line formed in a subsequent step and the storage node contact, a spacer is formed on a sidewall of the first opening. The spacer isolates the bit line from the storage node contact. Thus, problems caused by overlap margin between the bit line and the storage node plug do not occur. Then, a bit line is formed in the opening to make contact with the bit line contact. A third insulating layer is formed to cover the second insulating layer and the bit line. The third insulating layer, the cap layer, and the second insulating layer are patterned to form a second opening exposing the storage node contact. A conductive layer is formed in the second opening.
In the invention, because the storage node plug is formed before the formation of the bit line, there is a sufficient space for forming the storage node plug. The storage node plug and the storage node contact are together used as a contact. That is, the contact is formed by first forming the storage node contact, and then forming the storage node plug. Thus, it resolves difficulties in forming the contact with a high aspect ratio. The tolerance window for forming the bit line is increased. There is no additional mask for forming the bit line in the present invention. Thus, it simplifies the fabrication process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5362666 (1994-11-01), Dennison
patent: 5641694 (1997-06-01), Kenny
patent: 5858831 (1999-01-01), Sung
patent: 5858837 (1999-01-01), Sakoh et al.
patent: 5936272 (1999-08-01), Lee
Huang Jiawei
J. C. Patents
Tran Binh X.
United Micoelectronics Corp.
Utech Benjamin L.
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