Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-02-23
2000-08-22
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438597, 438647, 438649, H01L 213205
Patent
active
061071757
ABSTRACT:
A method of a method of fabricating a contact. A substrate having a plurality of gates and a plurality of lightly doped source/drain regions is provided. A dielectric layer is formed and patterned to form a self-align contact window to expose a first lightly doped source/drain region of said lightly doped source/drain regions, and to form a first spacer on a side wall of a first gate of said gates simultaneously. An ion implantation is performed by using the first spacer as a mask, so that a first heavily doped source/drain region is formed in the first lightly doped source/drain region. A doped poly-silicon layer is formed over the substrate, and a metal silicide layer is formed on the doped poly-silicon layer. The doped poly-silicon and the metal silicide layer are patterned to form a self-align contact.
REFERENCES:
patent: 5480837 (1996-01-01), Liaw et al.
patent: 5843815 (1998-12-01), Liaw
Wolf et al. ( Silicon Processing for the VLSI Era, vol. 1, p. 181, 1986.
Chien Sun-Chieh
Lin Han
Lin Jengping
Bowers Charles
Lee Hsien-Ming
United Microelectronics Corp.
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