Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-06-04
2001-01-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S296000, C438S305000, C438S306000, C438S424000, C438S437000, C438S685000
Reexamination Certificate
active
06180515
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of a fabricating a semiconductor device, in particular, to a method of fabricating a self-align contact window with silicon nitride side wall spacers. The present invention can be utilized in photolithography process and etching process to increase the accuracy of forming the contact window.
DESCRIPTION OF THE PRIOR ART
With the rapid development of integrated circuits technologies, there has been a trend to reduce the scale of a device. Thus, semiconductor technologies have increased the integrated circuit density on a chip. The semiconductor devices manufactured in and on the semiconductor substrate are very closely spaced. The alignment, lithography technologies are more important than ever due to the density of the packing density is continuously increased. Especially, the tolerance of self-align contact process is degrade, it is because that the contact window is reduced by scaling down the dimension of the features formed on a wafer.
The prior art meets a problem during the formation of self-align contact (SAC), as shown in FIG.
1
. Polysilicon gate electrodes
3
are formed on a semiconductor substrate
1
. A cap layer
5
is formed on the top surface of the gate electrodes
3
. Typically, the cap layer
5
is comprised of silicon oxide and is used as an etching barrier. Side wall spacers
7
composed of silicon oxide are formed on the side walls of the gate electrode
3
. Active regions
9
, such as source and drain, are formed in the substrate
1
adjacent to the gate electrodes
3
. Thick field oxide regions
11
are created for providing isolation between devices. A dielectric layer
13
composed of silicon oxide is formed on the gate electrode
3
for the purpose of isolating.
The field oxide regions
11
are formed on the semiconductor substrates
1
. Then, a silicon dioxide layer and a polysilicon layer
3
are respectively formed on the field oxide
11
and the semiconductor substrates
1
to act as the gate structure. Successively, a silicon nitride layer is deposited on the polysilicon layer. Followed by patterning a photoresist on the silicon nitride layer, the polysilicon layer, and the silicon oxide layer, an etching process is used to etch the polysilicon layer and silicon oxide layer. After the etching process, the gate electrodes
3
are formed, as shown in FIG.
2
.
Turning to
FIG. 3
, a silicon oxide layer
7
is deposited by using an atmosphere pressure chemical vapor deposition (APCVD) on the gate electrodes
3
and the cap layer
5
. An isotropic etching is used to form sidewall spacers
7
of the gate electrodes
3
, as shown in FIG.
4
. Then, ion implantation is used to form source and drain
9
. Next, a dielectric layer
13
is formed on the gate electrode
3
, cap layer
5
and the side wall spacers
7
by using low pressure chemical vapor deposition (LPCVD). A photoresist
15
, as shown in
FIG. 5
, is patterned on the dielectric layer
13
a.
Then, a dry etching is performed to etch the dielectric layer
13
a
for forming a contact window. The photoresist is then removed, as shown in FIG.
6
.
Unfortunately, the gate electrode
3
is generally exposed during the dielectric layer
13
is etched to form the contact window. The exposed gate electrodes
3
may cause gate leakage problem, for example, the gate
3
contacts with a subsequent polysilicon layer which contacts with the source/drain. The issue was caused by the cap layers
5
, spacers
7
are etched during above etching step to form the contact window.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating an integrated circuit having self align contact window and that can overcome the problem of photographic techniques.
It is an another object of the present invention to provide a method for fabricating self align contact window with silicon nitride side wall.
A gate oxide layer, a polysilicon layer are respectively deposited on a substrate. A first silicon nitride layer is then formed on the polysilicon layer to act as a cap layer. Then, the gate oxide, the polysilicon layer and the first silicon nitride layer are etched to form a gate structure using a first photoresist as an etching mask. Subsequently, a first silicon dioxide layer is formed on the surface of the gate structure. The first silicon nitride layer is used to reduce the stress between the polysilicon gate and a subsequent silicon nitride layer. A second silicon nitride layer is formed to on the first silicon dioxide layer. Next, a second silicon dioxide layer is formed on the second silicon nitride layer by using a chemical vapor deposition. Then, an etching technique is used to form the side-wall spacers. The side-wall spacers composed of silicon nitride layer and silicon dioxide layer are used as etching barriers to prevent the polysilicon gate from being exposed during the formation of a contact window using the etching step. A dielectric layer is formed on the cap layer, side-wall spacers and silicon dioxide layer. An etch with high selectivity is used to etch the dielectric layer to create a contact hole.
In the second embodiment, a gate oxide layer, a polysilicon layer are respectively deposited on a substrate. An etching step is performed to etch the gate oxide the polysilicon layer after the polysilicon layer is formed. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then, a first silicon nitride layer is patterned on the first silicon dioxide layer, over the top of the polysilicon layer. The thickness and the reaction temperature of the silicon dioxide layer are respectively 30-200 angstroms, 800-950 centigrade degrees. Then, a second silicon nitride layer is formed on the first silicon dioxide layer and the first silicon nitride layer. Next, a second silicon dioxide layer is formed on the second silicon nitride layer by using a chemical vapor deposition. Then, an etching technique is used to form the side-wall spacers. The side-wall spacers composed of silicon nitride layer and silicon dioxide layer are used as etching barriers to preventing the polysilicon gate from being exposed during the formation of a contact window using the etching step. A dielectric layer is formed on the cap layer, side-wall spacers and silicon dioxide layer. An etch with high selectivity is used to etch the dielectric layer to create a contact hole.
REFERENCES:
patent: 5591672 (1997-01-01), Lee et al.
patent: 5950090 (1998-11-01), Chen et al.
Berry Renee′ R.
Merchant & Gould P.C.
Nelms David
United Microelectronics Corp.
LandOfFree
Method of fabricating self-align contact window with silicon... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating self-align contact window with silicon..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating self-align contact window with silicon... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2518480