Method of fabricating polysilicon thin film transistor

Details Method of fabricating polysilicon thin film transistor Method of fabricating polysilicon thin film transistor

2002-12-06

2004-04-27

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S151000, C438S164000, C438S166000, C438S486000, C438S491000

Reexamination Certificate

active

06727122

ABSTRACT:

This application claims the benefit of Korean Application Nos. 2001-87728, 2001-87729, 2001-87730, and 2001-87731, all filed on Dec. 29, 2001 in Korea, all of which are hereby incorporated by reference.
This application also incorporates by reference the following three (3) U.S. patent applications that are filed concurrently with the filing of the instant application:
(1 ) Application Ser. No. 10/310,965, filed Dec. 6, 2003, entitled “Method of Fabricating Polycrystalline Thin Film Transistor,” of Inventors: Hyen-Sik SEO, Binn KIM, and Jong-Uk BAE;
(2) Application Ser. No. 10/310,964, filed Dec. 6, 2003, entitled “Method of Fabricating Polycrystalline Thin Film Transistor,” of Inventors: Binn KIM, Jong-Uk BAE, and Hae-Yeol KIM; and
(3) Application Ser. No. 10/310,966, filed Dec. 6, 2003, entitled “Method of Fabricating Polycrystalline Thin Film Transistor,” of Inventors: Hyen-Sik SEO, Binn KIM, and Jong-Uk BAE.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of crystallizing amorphous silicon, and more particularly, to a method of fabricating a polycrystalline silicon thin film transistor (TFT). Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving electrical characteristics of the thin film transistor.
2. Discussion of the Related Art
In a conventional process for forming a polycrystalline silicon layer, an intrinsic amorphous silicon layer is formed on an insulating substrate by using a Plasma Chemical Vapor Deposition (PCVD) method or a Low Pressure Chemical Vapor Deposition (LPCVD) method. After the amorphous silicon layer has a thickness of about 500 Å (angstroms), it is re-crystallized into a polycrystalline silicon layer by using a crystallization method. The crystallization method is generally classified into one of an Excimer Laser Crystallization (ELC) method, a Solid Phase Crystallization (SPC) method, a Metal Induced Crystallization (MIC) method, and a Metal Induced Lateral Crystallization (MILC).
In the ELC method, an insulating substrate having an amorphous silicon layer formed thereon is heated to a temperature of about 250° C. An excimer laser beam is then applied to the amorphous silicon layer to form a polycrystalline silicon layer. In the SPC method, the amorphous silicon layer is heat-treated at a high temperature for a long time to be crystallized into a polycrystalline silicon layer. In the MIC method, a metal layer is deposited on the amorphous silicon layer and the deposited metal is used for crystallization. In the MIC method, a large-sized glass substrate can be used as an insulating substrate. In the MILC method, a metal is first formed on the amorphous silicon layer, and then the amorphous silicon layer is crystallized. Also in the MILC method, an oxide pattern is formed on a predetermined active portion of the amorphous silicon layer. The amorphous silicon layer becomes polycrystalline silicon by a lateral growth of grains.
The Excimer Laser Crystallization (ELC) method has also been used with some advantages in annealing amorphous silicon. The excimer laser allows areas of an amorphous silicon film to be exposed to very high temperatures for very short periods of time. Theoretically, this offers a possibility of annealing the amorphous silicon at an optimum temperature (less than 400 degrees Celsius) without degrading the underlying substrate upon which the silicon amorphous film is mounted. However, use of this method has been limited by the lack of control over some of the process steps. Typically, an aperture size of the laser is relatively small. Due to the aperture size, power of the laser, and thickness of the amorphous silicon film, multiple laser passes or shots may be required to complete an annealing process. Since it is difficult to precisely control the laser, the multiple shots introduce non-uniformities into the annealing process. Further, the substrates must be annealed serially in a furnace rather than simultaneously. As a result, TFTs made by the ELC method are significantly more expensive.
In the SPC method, a buffer layer is formed on a quartz substrate that can stand a temperature higher than 600° C. The buffer layer serves to prevent a contamination from the quartz substrate. Thereafter, an amorphous silicon layer is deposited on the buffer layer and is sufficiently heat-treated in a furnace at a high temperature so as to form a polycrystalline silicon layer. However, because the SPC method is performed at the high temperature for a long period of time, it is difficult to acquire a desired crystalline silicon phase.
In the process of SPC method, because the crystalline grains develop without a continuous directionality, the polycrystalline silicon layer may have an irregular surface. In a thin film transistor, a gate insulating layer covers the polycrystalline silicon layer. Therefore, if the polycrystalline silicon layer has an irregular surface, the gate insulating layer is also irregularly formed, thereby decreasing a breakdown voltage of the thin film transistor. In addition, the size of the polycrystalline silicon grains formed by the SPC method are very irregular, thereby deteriorating electrical characteristics of a device using the polycrystalline silicon layer. Furthermore, the quartz substrate used for the SPC method is very expensive, thereby increasing the fabrication costs.
Unlike the SPC method that uses an expensive quartz substrate, the MIC method and the MILC method may utilize a relatively inexpensive glass substrate for forming polycrystalline silicon. In the MIC method and the MILC method, however, metal impurities may remain in the polycrystalline silicon network, thereby deteriorating the quality of the polycrystalline silicon layer. To alleviate this residual impurity problem, the conventional art employs the following method, which will be described with reference to
FIGS. 1A
to
1
C and
2
A to
2
E.
FIGS. 1A
to
1
C are perspective views illustrating process steps of forming a polycrystalline silicon layer according to the conventional art.
Referring to
FIG. 1A
, a buffer layer
12
and an amorphous silicon (a-Si:H) layer
4
are sequentially deposited on a substrate
10
. The buffer layer
12
is silicon nitride (SiN
x
) or silicon oxide (SiO
2
), and prevents alkali substances included in the substrate
10
from spreading into the amorphous silicon layer
4
. Thereafter, the amorphous silicon layer
4
is dehydrogenated by a heat-treatment.
Referring to
FIG. 1B
, a catalytic metal
16
is formed on the surface of the amorphous silicon layer
4
. For the catalytic metal
16
, Nickel (Ni), Lead (Pb) or Cobalt (Co) is preferably employed. An ion shower method, an ion doping method, a sputtering method or a chemical vapor deposition (CVD) method is employed for the formation of the catalytic metal
16
. After forming the catalytic metal, the amorphous silicon layer
4
is heated and then converted into a polycrystalline silicon layer
15
as shown in FIG.
1
C.
FIGS. 2A
to
2
E are cross-sectional views illustrating process steps of forming a thin film transistor having a polycrystalline silicon layer according to the conventional art.
Referring to
FIG. 2A
, a buffer layer
2
is first formed on the substrate
10
. Thereafter, a polycrystalline silicon layer is formed on the buffer layer
2
using the process mentioned with reference to
FIGS. 1A
to
1
C, and then patterned to form an island-shaped active layer
8
.
Referring to
FIG. 2B
, a gate insulation layer
11
is formed on the buffer layer
2
to cover the active layer
8
. The gate insulation layer
11
is made of silicon nitride (SiN
x
), silicon oxide (SiO
2
) or Tetra Ethoxy Silane (TEOS), for example. Thereafter, a gate electrode
12
is formed on the gate insulation layer
11
and over the active layer
8
. The active layer
8
is divided into two areas: a first active area
14
that is an intrinsic silicon area, and second active areas
16
and
17
wherein impurity ions are to be doped. The second active areas

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