Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-04-19
2002-06-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C125S011020
Reexamination Certificate
active
06399417
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to BGA (Ball Grid Array) semiconductor packaging technology, and more particularly, to a method of fabricating a set of plated circuit lines, including contact fingers, electrically-conductive traces, and solder-ball pads, over a BGA substrate.
2. Description of Related Art
BGA (Ball Grid Array) is an advanced type of semiconductor packaging technology which is characterized by the use of a substrate as chip carrier whose front side is used for mounting one or more semiconductor chips and whose back side is provided with a grid array of solder balls. During SMT (Surface Mount Technology) process, the BGA package can be mechanically bonded and electrically coupled to an external printed circuit board (PCB) by means of these solder balls.
A BGA substrate typically has a front surface formed with a plurality of contact fingers and electrically-conductive traces and a back surface formed with a plurality of solder-ball pads which are electrically connected through vias to the electrically-conductive traces on the front surface. Each of the contact fingers together with its connected electrically-conductive trace and solder-ball pad, connote a circuit lie for external connection. Traditionally, in order to allow these circuit lines to have increased bondability and electrically conductivity, they are typically plated with nickel and gold (Ni/Au).
A conventional method of fabricating plated circuit line over a BGA substrate is illustratively depicted in the following with reference to
FIGS. 1A-1C
(note that
FIGS. 1A-1C
are simplified schematic diagrams showing only a small number of components related to the invention for demonstrative purpose and which are not drawn to actual sizes and scales in practical applications; the actual circuit layout may be much more complex).
Referring to
FIGS. 1A-1B
, this conventional BGA package includes: (a) a substrate
110
whose front surface is used to mount a semiconductor chip
120
, and whose back surface is used to mount a ball grid array
130
(since the semiconductor chip
120
and the ball grid array
130
are to be mounted later, they are shown in dotted lines in FIG.
1
A); (c) a plurality of contact fingers
140
provided on the front surface of the substrate
110
and ground the semiconductor chip
120
to serve as electrical-connecting points for the semiconductor chip
120
; (d) a plurality of electrically-conductive traces
150
, which are provided on the front surface of the substrate
110
and electrically connected to the contact fingers
140
; (e) a plurality of solder-ball pads
160
provided on the back surface of the substrate
110
; (f) a plurality of electrically-conductive vias
170
in the substrate
110
for electrically connecting the solder-ball pads
160
to the electrically-conductive traces
150
.
In addition, in order to facilitate a plating process on the contact fingers
140
, and the solder-ball pads
160
, a common plating bus
180
is ,provided on the substrate
110
, which includes a plurality of branched plating lines
191
connected respectively to each of the electrically-conductive traces
150
.
During plating process, the plating electrical current can be applied to the plating bus
180
and then distributed over the branched plating lines
181
to each of the contact fingers
140
and the solder-ball pads
160
.
Referring further to
FIG. 1C
, as the plating process is completed, it is then required to break each of the branched plating lines
181
from the plating bus
180
by means of a cutting blade (not shown).
One drawback to the forgoing circuit layout scheme, however, is that, for each of the electrically-conductive traces
150
, it is required to provide a dedicated branched plating line. In the case of
FIGS. 1A-1C
, for example, since there are five electrically-conductive traces
150
, it is required to provide a total of 5 branched plating lines
181
, which would make the layout design work quite difficult in routability. Moreover, such a great number of the branched plating lines
181
would cause mutual inductive interference therebetween, undesirably degrading the electrical performance of the signal transmission over these circuit lines.
One conventional method to break the branched plating lines
181
from the plating bus
180
is to perform a selective substrate etch-back process in which a corrosive etchant and a photoresist mask are used to etch back into the jointed portions between the plating bus
180
and the branched plating lines
181
.
One drawback to the forgoing method, however, is that the etchant being used in the etch-back process would easily cause contamination to the substrate surface, which would adversely degrade the quality of the resulted package assembly on the substrate. Moreover, the disposal of the waste etchant after use would be a problem that is environmentally-unfriendly. Still one drawback to the forgoing method is that, since the points selected for etch-back are restricted to some areas only, it would cause the circuit lines to be lengthily routed over the BGA substrate, undesirably increasing the required layout area.
One solution to the foregoing problem is to utilize the so-called Gold Pattern Plating (GPP) technology, which allows the use of no branched plating lines over the BGA substrate, so that the above-mentioned drawbacks are resolved. The GPP technology is well-known in the semiconductor industry, so description thereof will not be further detailed.
One drawback to the utilization of the GPP technology, however, is that, after the contact fingers
140
and the solder-ball pads
160
have been gold-plate it would nevertheless require the use of corrosive etchant for subsequent pattern definition to form the electrically-conductive traces
150
, undesirably causing contamination to the gold-plated contact fingers
140
and the solder-ball pads
160
, thus degrading the quality of subsequent wire bonding and solder ball implantation over gold-plated contact fingers
140
and the solder-ball pads
160
. In addition, since the, GPP technology is highly complex in process which includes repetitive masked pattern definition steps, its implementation is highly cost-ineffective, roughly 1.3 to 1.5 times more costly than the use of other technologies.
The ROC Invention Patent No. 388970, published on May 1, 2000, teaches the use of laser means to break apart integrally-connected circuit lines into individual ones. This method, however, is considerably costly to implement since the required laser equipment is quite expensive to purchase.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a new method of fabricating plated circuit lines over BGA substrate, which would cause no contamination to the contact fingers and the solder-ball pads, so as to allow the finished BGA package more assured in quality and reliability.
It is another objective of this invention to provide a new method of fabricating plated circuit lines over BGA substrate, which allows the use of a reduced layout area for the circuit lines and also allows high routability.
It is still another objective of this invention to provide a new method of fabricating plated circuit lines over BGA substrate, which is more convenient and cost-effective to implement than the prior art.
In accordance with the foregoing and other objectives, the invention proposes a new method of fabricating plated circuit lines over BGA substrate.
The method of the invention is characterized by that contact fingers, electrically-conductive traces, and solder-ball pads on the BGA substrate are interconnected with provisional bridging lines; and then, each integrally-connected group of the contact fingers, the electrically-conductive traces, and the solder-ball pads is connected via a branched plating line to a common plating bus. During plating process, the plating electrical current can be applied to the plating bus and then distributed over these branched plating lines to all of the contact fingers and t
Lee Wen Cheng
Liao Chih-Chin
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Le Thao P
Nelms David
LandOfFree
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