Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2011-07-19
2011-07-19
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S593000, C438S742000, C438S942000, C438S586000, C257SE21192, C257SE21210, C257SE21645, C257SE21646
Reexamination Certificate
active
07981786
ABSTRACT:
A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.
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Cho Heung Jae
Joo Moon Sig
Kim Yong Top
Park Ki Seon
Pyi Seung Ho
Garber Charles D
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Sene Pape
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