Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-03
2001-10-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S639000, C438S700000
Reexamination Certificate
active
06300238
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an integrated circuit (IC) process. More particularly, the present invention relates to a method for fabricating a node contact opening.
2. Description of Related Art
Conventionally, in the IC process for dynamic random access memory (DRAM), an oxide layer is deposited after the formation of the metal oxide semiconductor (MOS). A bit line, which couples electrically with the substrate, is formed on the oxide layer before performing the capacitor process. A further oxide layer is deposited on the bit line and partially removed by photolithography and etching to form a node contact opening. As the node contact opening is etched for a longer duration due to its higher aspect ratio, a thicker pattern photoresist is required to adequately reduce the pattern distortion, which occurs during the long etching process. However, the thicker pattern photoresist has inevitably caused the problem of poorer focus window.
As the device size becomes smaller, the bit line is also easily exposed during the etching for the node contact opening, so that a short-circuiting occurs between the subsequently formed capacitor and the bit line. Although a silicon nitride spacer is formed on the sidewall of the opening, the substrate may still be exposed in the etching environment during the etching step for forming the silicon nitride spacer. This increases the possibility of the single cell substrate being damaged, thus influencing the reliability of the device.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a node contact opening. A thinner pattern photoresist is used to improve the focus window of the photoresist in the photolithography.
The method provided in the present invention prevents not only the short-circuiting between the capacitor and the bit line, but also protects the substrate exposed by the node contact opening from more damage.
As embodied and broadly described herein, the invention provides a fabrication method for a node contact, which method involves forming an insulating layer on the substrate, while a bit line which contacts the substrate is formed on the insulating layer. A conformal second insulating layer that serves as an etching stop layer is formed to cover the bit line and the first insulating layer. A third insulating layer is then formed on the second insulating layer to isolate the subsequently formed capacitor and bit line. A pattern mask is formed on the third insulating layer, while the pattern of the mask is transferred into the third insulating layer for subsequent etching, so that an opening is formed in the third insulating layer. After the second insulating layer in the opening is removed, a spacer is formed on a sidewall of the opening. With the pattern mask and the spacer serving as an etching mask, the first insulating layer below the bit line is etched until the opening is extended through to the substrate, so that a contact opening which connects the capacitor and the substrate is formed.
The photoresist is used together with the pattern mask during the formation of the node contact opening, so a thinner pattern photoresist is patterned to improve the focus window of the photoresist in the etching process. Since the spacer is formed on the sidewall of the opening during the first stage etching for the node contact opening, the spacer can also serve as an electrical isolation while the size of the node contact opening in the substrate is further reduced. This is the case even when the bit line is exposed during the formation of the opening. Furthermore, the substrate is protected from more damage because the spacer is not formed after the formation of the node contact opening.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5933755 (1999-08-01), Lee
patent: 6033980 (2000-03-01), Liou et al.
patent: 6087216 (2000-07-01), Wang
patent: 6090663 (2000-07-01), Wu
Chen Terry Chung-Yi
Lee Tong-Hsin
Fourson George
Garcia Joannie Adelle
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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