Semiconductor device manufacturing: process – Masking – Subphotolithographic processing
Patent
1996-12-31
2000-02-08
Niebling, John F.
Semiconductor device manufacturing: process
Masking
Subphotolithographic processing
438286, 438585, H01L 213205
Patent
active
060228156
ABSTRACT:
A method of fabricating minimum size and next-to-minimum size electrically conductive members using a litho-less process is disclosed. A substrate is provided, and a layer of gate dielectric material is formed on the substrate. A layer of electrically conductive material is formed over the gate dielectric material. A first mask is used to form a hard mask. A layer of first spacer material is deposited over the existing structures, and the layer of first spacer material is etched back to form spacers adjacent to the hard mask. The width of the first spacers determines the minimum size gate length. A layer of second spacer material is deposited over the existing structures, including the hard mask and first spacers. The layer of second spacer material is etched back to form a second set of spacers adjacent to the first spacers. The width of the first and second spacers together determine the next-to-minimum size gate length. A second mask is used to protect the portion of the second spacers which are to be used to define next-to-minimum size gates, and the unprotected second spacers and the hard mask are removed. The exposed electrically conductive material is removed. The remaining spacers are then removed, leaving minimum size and next-to-minimum size gates.
REFERENCES:
patent: 4400865 (1983-08-01), Goth et al.
patent: 5013680 (1991-05-01), Lowrey et al.
patent: 5017515 (1991-05-01), Gill
patent: 5593813 (1997-01-01), Kim
patent: 5923981 (1999-07-01), Qian
Fiegna et al, "Scaling the MOS Transistor Below 0.1 um: Methodology, Device Structures, and Technology Requirements", TED Jun. 1995, p. 941.
Kimura et al, "Short-Channel-Effect-Supressed Sub 0.1 um Grooved-Gate MOSFET's with W Gate", TED Jan. 1995, p. 94.
J. T. Jhorstmann et al, "Characterizatin of Sub-100 nm-MOS Transistors Fabricated by Optical Lithographer and a Sidewall-Etchback Process" NME, Sep. 1995.
Cheng Peng
Doyle Brian S.
Liang Chunlin
Qian Qi-De
Intel Corporation
Murphy John
Niebling John F.
Wells Calvin E.
LandOfFree
Method of fabricating next-to-minimum-size transistor gate using does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating next-to-minimum-size transistor gate using, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating next-to-minimum-size transistor gate using will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1681355