Method of fabricating MOSFET transistors with multiple...

Details Method of fabricating MOSFET transistors with multiple... Method of fabricating MOSFET transistors with multiple...

2003-04-30

2004-04-06

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S217000, C438S289000, C257S392000, C257S402000

Reexamination Certificate

active

06717221

ABSTRACT:

BACKGROUND
FIELD
The invention relates to generally complementary metal oxide semiconductor (CMOS) processing. CMOS circuits typically comprise n-type metal oxide semiconductor (NMOS) devices combined with p-type metal oxide semiconductor (PMOS) devices. Transistors made from NMOS and PMOS devices are typically referred to as metal oxide semiconductor field effect transistor (MOSFET) devices. More specifically, the invention relates to use of a single halo implantation to compensate the threshold voltage of a low threshold voltage transistor and enhance the threshold voltage of a high threshold voltage transistor to provide dual high and low threshold voltage for both NMOS and PMOS transistors.
BACKGROUND
Threshold voltage generally means the lowest gate voltage required to permit current to pass from a source to a drain in an insulated gate field effect transistor (FET). Threshold voltage is thus the level of voltage required to turn the transistor on. Threshold voltage is important because if it is too low, it is possible to suffer off state leakage.
Off state leakage is leakage current that occurs when the transistor is turned off. If zero volts are placed on the gate of the transistor, nominally, the transistor should be off and zero current should flow. If the gate is at zero volts, there is no inversion region and there should be no current. The source and drain should be like two back-to-back diodes. There may be a small amount of diode leakage, of course, particularly where the source and the drain are close together. There may be a certain amount depletion region extending from the source and the drain towards each other, because the critical dimension of the transistor, i.e., the gate length is reduced. If these depletion regions overlap, they may create source to drain leakage. The merging of these depletion regions may be defeated by an implant strengthening the depletion region beneath the gate. One side effect of such an implant is to raise the voltage required to turn the gate on, or raise the threshold voltage of the transistor.
One of the ways to dope the region under the gate between the source and drain to defeat off state leakage is called a halo implant. The halo implant, as is well known in the art, is an implant that is typically directed at the surface of the integrated circuit at an angle off the normal of 0° to 60°. In terms of a wafer fabrication technique, the halo implant is typically directed at the wafer from four different directions. For example, the implant could be directed at the wafer from the lateral directions (e.g. right and left direction) and the top and bottom direction. The implant typically will be directed at the gate from a direction over the source and another from over the direction of the drain. The implants from the right and left direction may take care of all transistors oriented in a single direction. Typically, however, there are transistors that are oriented 90° from other transistors. Giving these transistors halo implants will require implanting from the top and bottom. Thus, the four-direction implant will give halo implants to all insulated gate field effect transistors that are exposed.
One reason for implanting the halo implant after formation of the transistor is that the critical dimension or gate length of the transistor operates as a control in the variables required to establish threshold voltage. The critical dimension of these transistors varies slightly. However, even this slight variation can affect the threshold voltage boost required by the implant. A slightly longer critical dimension or gate length transistor will need a lower threshold voltage boost because the gate itself is separating the source from the drain leaving a large region between the source and drain which reduces the probability of source drain overlap. The larger critical dimension will also separate the halo implants while a smaller critical dimension transistor would allow more of the halo implants to join each other beneath the gate.
In addition, a source drain extension (SDE) implant is preformed after the gate is fabricated. The SDE implant moves the source and drain regions closer to each other and the gate, than the regular source drain implant by itself would. The limit of the source drain extension implant is typically defined by the critical dimension of the gate, i.e. gate length. Here again, a larger critical dimension keeps the source and drain farther apart, while a smaller CD allows the source and drain to extend closer together. The larger CD gate requires less halo implant beneath it, while a smaller CD gate requires a greater halo implant to control off state leakage. A greater halo implant tends to boost the threshold voltage.
Typically, the halo implantation process requires a procedure of four maskings and implantations in the formation of a dual threshold voltage CMOS circuit. The first masking and implantation is used to expose and implant the high threshold voltage NMOS device. This procedure includes an n
−
SDE implant, typically at 0° from the normal of the surface of the wafer and a p halo implant. The next masking step uncovers the low threshold voltage NMOS transistor which would require an n
+
SDE and a lower dose p
−
halo implant. The third masking and implantation operation would fabricate the high threshold voltage PMOS transistor and would entail a p
+
SDE implantation at 0° from the normal of the surface of the wafer and an n halo implantation. The final masking operation would fabricate the low threshold voltage PMOS and would require a p
+
SDE normal implantation and an n
−
halo implantation. The difficulty with four masking and implantation operations is the increased cost and process complexity


REFERENCES:
patent: 5747855 (1998-05-01), Dennison et al.
patent: 6096611 (2000-08-01), Wu
patent: 6426261 (2002-07-01), Fujii et al.
patent: 6552394 (2003-04-01), Ahmad et al.

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