Method of fabricating MOSFET devices

Details Method of fabricating MOSFET devices Method of fabricating MOSFET devices

1997-01-27

1997-12-30

Trinh, Michael

Fishing, trapping, and vermin destroying

437 41SW, 437 44, 437 59, 437200, H01L 218238

Patent

active

057029725

ABSTRACT:
A method for improving the source/drain resistance in the fabrication of an integrated circuit device is described. Gate electrodes are formed on the surface of a semiconductor substrate. Lightly doped regions are implanted into the semiconductor substrate using the gate electrodes as a mask. First spacers are formed on the sidewalls of the gate electrodes. Second spacers are formed on the sidewalls of the first spacers. Heavily doped source and drain regions are implanted into the semiconductor substrate using the gate electrodes and first and second spacers as a mask. Thereafter, the second spacers are removed. A titanium layer is deposited by chemical vapor deposition over the substrate whereby titanium silicide is formed overlying the gate electrodes and overlying the source and drain regions and whereby elemental titanium is deposited overlying the first spacers wherein the titanium silicide overlying the source and drain regions improves the source/drain resistance. The elemental titanium is removed. The substrate is annealed to transform all of the silicide into C54-phase TiSi.sub.2 and the fabrication of the integrated circuit device is completed.

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