Method of fabricating MOS field effect transistor

Details Method of fabricating MOS field effect transistor Method of fabricating MOS field effect transistor

1987-12-03

1989-06-13

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

148DIG50, 156649, 156653, 156657, 1566591, 156662, 437 78, 437105, 437112, 437228, 437 34, 437913, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

048389935

ABSTRACT:
A novel MOS field effect transistor which operates at high speed and with low power consumption has impurity doped source and drain regions deposited at 850.degree. C. or less by molecular layer epitaxial growth method. The molecular layer epitaxial growth is concurrently carried out with the control of impurity doping concentration so that the layers epitaxially deposited has a lightly doped region and a heavily doped region. Since the thickness of the growth layer can be controlled with a degree of accuracy on the order of an atom layer and thermal diffusions can remarkably be reduced by the low deposition temperature, an overlap of a gate over each of the source and drain regions can be reduced to 500 .ANG. or less.

REFERENCES:
patent: 4636269 (1987-01-01), Boland

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