Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-12-30
2004-11-23
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000, C438S617000
Reexamination Certificate
active
06821877
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a metal interconnection of semiconductor device and, more particularly, to a metal interconnection fabricating method comprising the step of performing a thermal treatment process prior to formation of bond pad openings.
2. Background of the Related Art
Generally, semiconductor products are manufactured through a wafer fabrication process, a semiconductor fabrication process, and an assembly process. In the semiconductor fabrication process, a process of forming a bond pad may be a final step. The bond pad is electrically coupled to a metal interconnection, and plays a role of a channel connecting electrically semiconductor devices formed on a semiconductor substrate with external devices. A passivation layer to protect the semiconductor devices formed on the substrate is formed after the formation of the bond bad. Then, openings to expose the bond pad are formed by removing some portion of the passivation layer.
FIGS. 1
a
through
1
e
illustrate, in cross-sectional views, the process steps for forming bond pad openings according to a prior art. Referring to
FIG. 1
a
, an underlying layer
11
on a semiconductor substrate having some predetermined devices is provided and a metal interconnection
12
is formed on the underlying layer
11
. An interlayer dielectric
13
is formed over the metal interconnection
12
and the underlying layer
11
. Some portion of the interlayer dielectric
13
is removed to expose some portion of the metal interconnection
12
. A bond pad
14
, which is coupled to the metal interconnection
12
exposed, is formed. Then, a passivation layer
15
is formed over the all structures including the bond pad
14
. The bond pad
14
generally comprises a metal layer
14
a
and a top metal layer
14
b
to form a multi-layered structure. The passivation layer
15
comprises oxide
15
a
such as PSG and nitride
15
b.
Referring to
FIG. 1
b
, a photoresist pattern
16
to make bond pad openings is formed on the passivation layer
15
. Referring to
FIG. 1
c
, in a first etching process, the nitride
15
b
is etched using the photoresist pattern
16
as an etch mask. The nitride
15
b
is etched by plasma etch using a mixture gas of CF
4
gas and O
2
gas. Then, as shown in
FIG. 1
d
, in a second etching process, the oxide
15
a
is etched using the photoresist pattern
16
as an etch mask and, successively, the top metal layer
14
b
of the bond pad
14
is etched. Therefore, the metal layer
14
a
of the bond pad
14
is exposed to form a bond pad opening
17
. The oxide
15
a
and the top metal layer
14
a
are etched by plasma etch using a mixture gas of CF
4
gas, Ar gas, and N
2
gas.
Referring to
FIG. 1
e
, the photoresist pattern
16
is removed by plasma etch using O
2
gas. A development treatment process using basic organics is performed to remove polymer remaining on the metal layer
14
a
of the bond pad
14
. Then, the formation of bond pad opening is completed.
Subsequently, a baking process is performed for the substrate with the bond pad opening. Here, the bond pad which is exposed to an electric furnace or an oven during the baking process is easily contaminated by materials outgassed from baking equipment or oxidized by thermal energy. A semiconductor device having the bond pad contaminated by organic materials cannot be used.
The organic materials are likely to be outgassed from the baking equipment. Particularly, in case of applying a process of baking the bond pad for 72 hours at 200° C., the contamination of the bond pad causes a very serious trouble. That is, the contaminated bond pad makes it impossible to perform a probe test and, therefore, the quality of semiconductor device fabricated cannot be measured. In addition, since it is impossible to perform wire bonding for the contaminated bond pad, a semiconductor device with the contaminated bond pad cannot be used.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a metal interconnection of semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of fabricating a metal interconnection that can settle the problem that a bond pad is easily contaminated by materials outgassed from baking equipment or oxidized by thermal energy, by performing a thermal treatment process prior to the formation of bond pad openings.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method of fabricating a metal interconnection of semiconductor device according to the present invention comprises the steps of:
forming a metal interconnection by depositing and patterning a metal layer on a substrate with some
predetermined structures;
forming a passivation layer over the substrate including the metal interconnection;
performing a thermal treatment process for the substrate with the passivation layer;
forming a bond pad by selectively etching the passivation layer so that some portion of the metal interconnection is exposed;
performing a probe test through the bond pad after grinding back side of the substrate with the bond pad; and
bonding a wire to the bond pad to connect the bond pad with an external circuit.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
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Anam Semiconductor Inc.
Estrada Michelle
Fourson George
Pillsbury & Winthrop LLP
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