Method of fabricating metal-insulator-metal capacitor and...

Details Method of fabricating metal-insulator-metal capacitor and... Method of fabricating metal-insulator-metal capacitor and...

2006-01-25

2010-06-08

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

Making passive device

Planar capacitor

C438S238000, C438S239000, C438S250000, C438S361000, C257S310000, C257SE21008, C257SE21019, C257SE21011

Reexamination Certificate

active

07732296

ABSTRACT:
In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresponding to a capacitor cell, on each of the lower electrodes to provide a plurality of MIM capacitor cells constituting one capacitor to which the same electric signal is applied.

REFERENCES:
patent: 6251740 (2001-06-01), Johnson et al.
patent: 6350694 (2002-02-01), Chang et al.
patent: 10-2002-0045891 (2002-06-01), None
patent: 10-2003-0050694 (2003-06-01), None
patent: 10-2003-0057640 (2003-07-01), None
Chung et al., “Flowable oxide CVD Process for Shallow Trench Isolation in Silicon Semiconductor”, Mar. 2004, Journal of Semiconductor Technology and Science, vol. 40 No. 1, pp. 45-51.

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