Method of fabricating lateral DMOS structure

Details Method of fabricating lateral DMOS structure Method of fabricating lateral DMOS structure

1993-03-15

1995-01-17

Fourson, George

Fishing, trapping, and vermin destroying

437 44, 437150, 437154, 437 45, 148DIG126, H01L 21265

Patent

active

053825365

ABSTRACT:
A lateral DMOS (LDMOS) transistor 10 is disclosed herein. In one embodiment, an n doped silicon layer 14 is provided and a field oxide region 24 is formed therein. A p doped D-well region 20 is formed in the silicon layer 14 and includes a p doped shallow, extension region 22 which extends from the D-well region 20 to a first side of the field oxide region 24. A first n doped source/drain region 16 is formed in the D-well region 20 and is spaced from the field oxide region 24. Also, a second n doped source/drain region 18 formed in the silicon layer 14 on a second side of the field oxide region 24. A gate region 26 is formed over the surface of the silicon layer 14 and over a portion of the first source/drain region 16, the D-well region 20, and a portion of the field oxide region 24.

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