Method of fabricating junction field effect transistor

Details Method of fabricating junction field effect transistor Method of fabricating junction field effect transistor

1989-11-24

1991-01-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 24, 437131, 437196, 437911, 357 22, 148DIG59, H01L 21265

Patent

active

049835360

ABSTRACT:
A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions. The germanium is intermixed with the underlying silicon to form a germanium-silicon composite. A rapid thermal anneal is performed to recrystallize the germanium-silicon composite. Alternatively, a single crystal epitaxial layer may be deposited on the silicon. Conventional metallization procedures are employed to produce ohmic source and gate contact members to the germanium-silicon composite or the epitaxial germanium of the source and gate regions. By virtue of the reduced bandgap provided by the presence of the germanium, the contact resistance of the device is reduced.

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Tamama, T., Voltage-Controlled Negative Resistance in a Submicron Vertical JFET, Solid State Electronics, Oct. 1984, pp. 855-866.
Growth, Nucleation & Electrical Properties of Molecular Beam Epitaxially Grown As-Doped Ge on Si Substrates, P. Sheldon et al., J. Vac. Sci. Technology A, vol. 4, No. 3, May/Jun. 1986.

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