Method of fabricating integrated circuit structures using replic

Details Method of fabricating integrated circuit structures using replic Method of fabricating integrated circuit structures using replic

1983-05-02

1986-02-25

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29576R, 148187, 156646, 156651, 156653, 156657, 1566591, 357 50, B44C 122, C03C 1500, C03C 2506

Patent

active

045727651

ABSTRACT:
A method of defining narrow regions in an underlying integrated circuit structure includes the steps of depositing a first layer of material 30 having selected etching characteristics on the underlying integrated circuit structure, depositing a second layer of material 32 having etching characteristics different from the first layer 30 on the first layer 30, anisotropically etching the first layer 30 and the second layer 32 from all of the underlying integrated circuit structure 26 except for a desired region having a periphery which includes the narrow region, forming a coating 35 of smoothing material over all of the underlying integrated circuit structure 26 except for the first layer 30, and isotropically etching the first layer 30 to remove it from the surface of the underlying integrated circuit structure 26 to thereby define the narrow region 36. Use of the process to fabricate a compact bipolar transistor structure is also disclosed.

REFERENCES:
patent: 3783047 (1974-01-01), Paffen et al.
patent: 4387145 (1983-01-01), Lehrer et al.

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