Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
1999-12-20
2002-08-06
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C438S003000, C438S240000
Reexamination Certificate
active
06429088
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods of forming capacitors, and specially to fabricating improved MOM and MOS capacitors with pinhole repair consideration when oxide conductors are used as part of the bottom or top electrode.
BACKGROUND OF THE INVENTION
Metal-oxide-metal (MOM) (also known as metal-insulator-metal (MIM)) or metal oxide semicondutor (MOS) capacitors involving high dielectric constant (K) oxide insulators, such as Ta
2
O
5
, are becoming more and more important in microelectronics. High-K oxide insulator MOM, or MIM, capacitors are used for memory in DRAM or as RF capacitors in mixed signal IC (integrated circuits). High-K MOS capacitors can form part of MOSFET devices.
When an oxide material insulator is deposited onto a metal/semiconductor layer or when a metal is deposited onto an oxide insulator, the metal/semiconductor layer tends to react with the oxide through a reduction reaction. This is especially true of the bottom metal electrode of a MOM capacitor, for example. This creates oxygen vacancies in the oxide insulator resulting in leakage current. This generation of oxygen vacancies by the reaction between the oxide insulator and the metal/semiconductor layer electrode also happens during annealing of the oxide insulator in an oxidizing ambient after the deposition of the oxide insulator. This limits the effect of the annealing in the reduction of oxygen vacancies and so leakage current. Other degradation of the electrical properties of the oxide insulator is also possible such as a reduced capacitance because of the formation of another insulating metal oxide film (or an oxide of semiconductor layer) of the metal/semiconductor layer electrode during the deposition of the oxide insulator or during the post-deposition annealing in an oxidizing ambient.
In an article entitled “A stacked capacitor technology with ECR plasma MOCVD (Ba,Sr)TiO
3
and RuO2/Ru/TiN/TiSix storage nodes for Gb-scale DRAM's,” IEEE Trans. Electron. Dev., vol. 44, pp. 1076-1083, Yamamichi et al. used RuO
2
/Ru as a conducting oxide between (Ba,Sr)TiO
3
(high-K oxide insulator) and TiN/TiSix
+
-poly (bottom electrode) in their capacitors.
U.S. Pat. No. 5,861,332 to Yu et al. describes a method of fabricating a capacitor of a semiconductor device which is capable of improving the chemical and thermal stability of lower electrodes. The chemical and thermal stability of the lower electrode is accomplished by forming a SrO film over a ruthenium dioxide (RuO
2
) film over a patterned ruthenium film, whereby the SrO and RuO
2
react to form a SrRuO
2
film interface during a high temperature deposition of a high dielectric film over the structure.
U.S. Pat. No. 5,877,062 to Horii describes a method of forming an integrated circuit capacitor having a protected diffusion barrier metal layer therein. The diffusion barrier metal layer inhibits parasitic migration of silicon from the polysilicon plug to the first electrically conductive layer. The capacitor dielectric layer is selected from the group Ta
2
O
5
, SrTiO
3
, BaTiO
3
, (Ba,Sr)TiO
3
, Pb(Zr,Ti)O
3
, SrBi
2
Ta
2
O
9
(SBT), (Pb, La)(Zr, Ti)O
3
and Bi
4
Ti
3
O
12
, etc.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating improved MOM and MOS capacitors by the use of a conductive metal oxide film between the oxide insulator and the top metal only.
Another object of the present invention is to provide a method of fabricating improved MOM capacitors by the use of a conductive metal oxide film between the oxide insulator and the bottom metal with or without the use of a conductive metal oxide film between the oxide insulator and the top metal.
Yet another object of the present invention is to provide a method of repairing pinholes in an oxide insulator layer when a conductive metal oxide film is inserted between the oxide insulator layer and the bottom metal layer.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a bottom metal layer is deposited. A high dielectric constant oxide insulator is deposited layer over the bottom metal layer. The structure is annealed in an oxidizing ambient to cause the exposed bottom metal to form a metal oxide partially filling the one or more pin hole defects to repair those pin hole defects. An upper oxide conductor layer is then deposited over the high dielectric constant oxide insulator layer. An upper metal layer is deposited over said upper oxide conductor layer.
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Yamamichi et al., “A stacked capacitor technology with ECR plasma MOCVD (Ba, Sr)TiO3and RuO2/Ru/TiN/TiSix storage nodes for Gb-scale DRAM's”, IEEE Trans. Electron. Dev., vol. 44, pp. 1076-1083.
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L.S.
Saile George O.
Stanton Stephen G.
Wilczewski Mary
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