Method of fabricating high-voltage junction-isolated semiconduct

Details Method of fabricating high-voltage junction-isolated semiconduct Method of fabricating high-voltage junction-isolated semiconduct

1997-01-31

2000-02-29

Booth, Richard

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

438514, 438526, 438527, H01L 2104

Patent

active

060308885

ABSTRACT:
A method of fabricating a junction-isolated semiconductor device is provided which includes the following steps. Within a first P-type buried region second N-type buried regions are formed. Over the first and second buried regions, an N-type epitaxial layer defining a surface of the device is grown. In the epitaxial layer, P-type isolation regions extending from the surface down to and in electric continuity with the first buried region and defining, with the first buried region, N-type wells incorporating the second buried regions is formed. And, P-type annular border regions in the epitaxial layer and to the side of the isolation regions are formed. The steps of forming isolation regions and annular border regions semiconducting regions being performed in a single step of selectively introducing doping ions.

REFERENCES:
patent: 4311532 (1982-01-01), Taylor
patent: 5156989 (1992-10-01), Williams et al.

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