Method of fabricating high voltage fully depleted SOI...

Details Method of fabricating high voltage fully depleted SOI... Method of fabricating high voltage fully depleted SOI...

2007-10-16

2010-06-29

Purvis, Sue (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29151, C257SE29273

Reexamination Certificate

active

07745879

ABSTRACT:
A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region is disposed a carrier recombination element, which abuts the gate structure and is electrically connected to the region via the channel. The drain region is lightly doped and ballasted to increase breakdown voltage. The FD SOI may be fabricated by forming a body with a thin silicon layer disposed on a buried oxide (BOX). Alternatively, the body may be formed using a partially depleted (PD) SOI where the region formed therein has a reduced thickness in comparison to the overall thickness of the PD SOI.

REFERENCES:
patent: 6413829 (2002-07-01), Yu
patent: 2003/0218193 (2003-11-01), Hayashi et al.
patent: 2004/0014304 (2004-01-01), Bhattacharyya
patent: 2007/0025034 (2007-02-01), Chaudhary et al.

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