Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Reexamination Certificate
2010-03-26
2011-10-18
Louie, Wai Sing (Department: 2814)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
C257S021000, C257S197000, C257S199000, C257S200000, C257S201000, C438S318000
Reexamination Certificate
active
08039351
ABSTRACT:
A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>.
REFERENCES:
patent: 3569800 (1971-03-01), Collins
patent: 5344785 (1994-09-01), Jerome et al.
patent: 5506427 (1996-04-01), Imai
patent: 6509242 (2003-01-01), Frei et al.
patent: 7037798 (2006-05-01), Adam et al.
patent: 7504704 (2009-03-01), Currie et al.
patent: 2003/0012925 (2003-01-01), Gorrell
patent: 2006/0105533 (2006-05-01), Chong et al.
patent: 2007/0238276 (2007-10-01), Liu et al.
U.S. Appl. No. 11/969,448, filed Jan. 4, 2008, Notice of Allowance and Fees Due dated Mar. 10, 2010.
U.S. Appl. No. 11/969,448, filed Jan. 4, 2008, Office Action dated Sep. 16, 2009.
Adam Thomas N.
Krishnasamy Rajendran
Hoffman Warnick LLC
International Business Machines - Corporation
Jahan Bilkis
Louie Wai Sing
Petrokaitis Joseph
LandOfFree
Method of fabricating hetero-junction bipolar transistor (HBT) does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating hetero-junction bipolar transistor (HBT), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating hetero-junction bipolar transistor (HBT) will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4284568