Method of fabricating gate structure to reduce stress...

Details Method of fabricating gate structure to reduce stress... Method of fabricating gate structure to reduce stress...

2000-01-31

2001-09-18

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S298000, C438S589000, C438S595000

Reexamination Certificate

active

06291330

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a fabrication method of a gate structure so as to reduce stress production.
2. Description of Related Art
In a high integration semiconductor process, a metal oxide semiconductor transistor, known as MOS transistor in short, has been adopted to replace the role played by the conventional bipolar transistor in conducting current in the semiconductor device. The MOS transistor generally comprises of a gate structure to which the input signal is normally applied, and a source/drain region, across which the output voltage is developed, and through which the output current flows.
A conventional fabrication process for the gate structure includes forming a gate oxide layer on an active region of a substrate defined by isolation structures. A gate stack comprising of a polysilicon layer, a metal silicide layer, and a nitride layer was hen formed on the gate oxide layer. The process continued by forming a buffer oxide layer on sidewalls of the gate stack, and forming a nitride spacer on sidewalls of the buffer oxide layer.
FIGS. 1A through 1E
illustrate the conventional fabrication process for the gate structure and some problems created when the buffer oxide layer was formed using different oxidation methods.
Referring to
FIG. 1A
, a substrate
100
is provided with an active region (not shown) defined by isolation structures
102
in the substrate
100
. A gate oxide layer
104
is then grown on the substrate
100
, followed by formation of a gate stack
111
. The gate stack
111
comprises of a doped polysilicon layer
106
to provide an electrical conduction, a metal silicide layer
108
to enhance a transmission speed, and a nitride layer
110
for passivation. The method for forming the gate stack
111
includes depositing in sequence the doped polysilicon layer
106
, the metal silicide layer
108
, and the nitride layer
110
on the gate oxide layer
104
, followed by patterning the three layers to obtain the gate stack
111
on the active region.
Referring to
FIG. 1B
, a buffer oxide layer
112
a
is formed to cover the gate stack
111
and the gate oxide layer
104
. The buffer oxide layer
112
a
is known to reduce a stress induced by a nitride spacer (not shown), and one common approach for forming the buffer oxide layer
112
a
includes low-pressure chemical vapor deposition (LPCVD).
Referring to
FIG. 1C
, another nitride layer (not shown) for forming a nitride spacer
114
is formed on the buffer oxide layer
112
a
. The nitride spacer
114
is formed using an etch-back process to remove the excess nitride layer. An etch-back process is further performed to remove the excess buffer oxide layer
112
a
on the nitride layer
110
. A lightly doped drain (LDD) implantation is performed to dope ions into the substrate
100
for forming a source/drain region
116
. However, the buffer oxide layer
112
a
formed as such creates a buffer oxide breakthrough problem when a self-aligned contact (SAC) opening is subsequently formed by etching. After forming a silicon oxide layer
118
for insulation, a large portion the buffer oxide layer
112
a
is also removed together with a part of the silicon oxide layer
118
, as shown in FIG.
1
C. This creates a notch that exposes the conductive material in the gate stack to a metal layer deposited in the subsequent process. As a result, an electrical problem, such as short circuit occurs in the fabrication process.
The process step described in
FIG. 1C
is different from FIG.
1
D and
FIG. 1E
only in terms of the oxidation approach for forming the buffer oxide layer, therefore similar process steps will not be described further herein. Referring to
FIG. 1D
, the buffer oxide layer
112
b
is formed on the gate oxide layer
104
and sidewalls of the metal silicide layer
108
and the polysilicon layer
106
. The buffer oxide layer
112
b
is formed by rapid thermal oxidation (RTO), so that the buffer oxide layer
112
b
formed on the gate oxide layer
104
is thicker than the buffer oxide layer
112
b
formed on the sidewalls of the metal silicide layer
108
and the polysilicon layer
106
. However, the buffer oxide layer
112
b
formed by RTO usually requires conditions, such as high temperature and short duration, which conditions would produce a stress that degrades the gate oxide layer. And besides the problem of gate oxide degradation, the fabrication process that includes RTO also incurs a high thermal budget.
FIG. 1E
, illustrates another approach for forming the buffer oxide layer
112
c
, where the buffer oxide layer
112
c
is grown by thin oxidation in a furnace (not shown). This method of oxidation inevitably creates problems such as oxide encroachment, where a part of buffer oxide layer
112
c
grows into the polysilicon layer
106
to damage the gate stack
111
. According to this oxidation, the buffer oxide layer
112
c
grown on the sidewall of the gate stack
111
is thicker. As a result, this reduces the critical dimension (CD) and deteriorates the refresh time of the semiconductor device.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a gate structure, which method reduces stress production induced by a nitride spacer.
As embodied and broadly described herein, the invention provides a fabrication method for the gate structure. A substrate is provided with isolation structures formed therein, wherein the isolation structure defines an active region in the substrate. A buffer oxide layer is formed on the substrate, followed by forming a nitride layer and mask oxide layer. The nitride layer and the mask oxide layer are then patterned to form a gate opening, wherein the gate opening delineates a gate stack, which is formed within the gate opening. A part of the buffer oxide layer exposed by the gate opening is removed, followed by forming a gate oxide layer. A polysilicon layer, a metal silicide layer, and a cap nitride layer are formed in sequence as the gate stack on the gate oxide layer. The mask layer is removed prior to a lightly doped drain (LDD) implantation that is performed to form a source/drain region. A nitride spacer is then formed on sidewall of the gate stack to complete the manufacture of the gate structure.
According to the present invention, the gate stack is formed after formation of the buffer oxide layer, therefore problems resulted from formation of the buffer oxide layer by different oxidation approaches are solved. Specifically, the present invention has advantages and benefits such as, low thermal budget for device implant, since it is not necessary to perform rapid thermal oxidation to grow buffer oxide layer on the gate stack. The invention is also free from sidewall oxidation issue because the gate stack is formed after the formation of the buffer oxide layer, so problems such as oxide encroachment, CD shrinkage, and refresh time deterioration no longer occur. In addition, the invention solves the problem of buffer oxide breakthrough during the etching step for forming a self-aligned contact (SAC) opening.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5688704 (1997-11-01), Liu
patent: 5786255 (1998-07-01), Yeh et al.
patent: 5851876 (1998-12-01), Jenq
patent: 5915181 (1999-06-01), Tseng
patent: 6090676 (2000-07-01), Gardner et al.
patent: 6107140 (2000-08-01), Lee et al.

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