Method of fabricating gate electrodes of twin-well CMOS device

Details Method of fabricating gate electrodes of twin-well CMOS device Method of fabricating gate electrodes of twin-well CMOS device

1998-04-24

2000-08-15

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

438711, 438712, 438714, 438734, 438735, 438742, H02L 2100

Patent

active

06103603&

ABSTRACT:
A multi-step dry-etching method that sequentially employs plasma etching and reactive ion etching process steps to form the pairs of adjacent, doped polysilicon gate electrodes of a twin-well CMOS device. The initial dry-etching process step uses to best advantage the speed of plasma etching to rapidly form pairs of adjacent p- and n-type gate-precursor features with substantially vertical sidewalls from the upper 50-80% of a doped polysilicon layer which lies on an insulating film. The gate-precursor features and, subsequently, the gate electrodes are formed from pairs of adjacent p- and n-type regions within the doped polysilicon layer which lie over pairs of adjacent n- and p-wells (the twin wells of the CMOS device), respectively, within a substrate. The subsequent dry-etching process step uses reactive ion etching to complete the formation of the pairs of adjacent, doped polysilicon gate electrodes from the remaining 50-20% of the etched, doped polysilicon layer without over-etching the insulating film.

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Journal of Vacuum Science & Technology B, "Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena," vol. 13. No. 2. Mar./Apr. 1995, pp. 214-226.

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