Method of fabricating dynamic random access memory capacitor

Details Method of fabricating dynamic random access memory capacitor Method of fabricating dynamic random access memory capacitor

1998-11-13

2000-08-01

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438254, 438397, 438398, H01L 2120

Patent

active

060966203

ABSTRACT:
A method of fabricating a capacitor. Isolation layers and conductive layers are formed alternately on a dielectric layer on a substrate. The conductive layers and the isolation layers are patterned to form an opening to expose a conductive region of the substrate. A spacer is formed on the sidewall of the conductive layers and the isolation layers exposed by the opening. The spacer is used as a mask to form a contact hole. The conductive layer on the dielectric layer is used as an etching stop layer. The isolation layers and the conductive layers are patterned. A conductive layer is formed to cover the substrate to cover the isolation layers and the conductive layers and to fill the contact hole. A portion of the conductive layers is removed to expose the spacer. The spacer and isolation layers are removed to expose the storage electrode formed by the conductive layers. A dielectric film layer and a cell electrode are formed in sequence over the substrate.

REFERENCES:
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5126810 (1992-06-01), Gotou
patent: 5206787 (1993-04-01), Fujioka
patent: 5817553 (1998-10-01), Stengl et al.
patent: 5851897 (1998-12-01), Wu
patent: 5904537 (1999-05-01), Wu
patent: 6020233 (2000-02-01), Kim
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M Drams", International Electron Devices Meeting, Dec. 1988, pp. 592-595.

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