Method of fabricating dual damascene structure

Details Method of fabricating dual damascene structure Method of fabricating dual damascene structure

1999-03-29

2001-11-06

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S597000, C438S631000, C438S675000, C438S687000

Reexamination Certificate

active

06313028

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabricating method of multi-layered interconnections. More particularly, the present invention relates to a method of fabricating a dual damascene structure.
2. Description of the Related Art
Due to the increased number of devices incorporated in a semiconductor circuit and the corresponding size reduction of the devices, material property is an important factor that affects device performance. For example, the material of the metallic multi-layered interconnections greatly affects resistance of the devices. Thus, in order to reduce the resistance, it is an important subject to select a suitable metallic material.
Copper has many good qualities such as a low resistivity and a high electromigration resistance. In addition, copper can be formed by chemical vapor deposition (CVD) or electroplating. Thus, copper is widely used in sub-micron process to form multi-layered interconnects. However, some problems still occur when using copper in sub-micron process. For example, copper is easily oxidized and eroded. It is difficult to pattern copper by dry etching. The adhesion between copper and dielectric materials is poor. Furthermore, copper easily diffuses into the dielectric materials so that the reliability of devices is decreased.
To solve the above-described problems, the conventional method uses a dual-damascene technique with a chemical-mechanical polishing step.
FIGS. 1A through 1C
are schematic, cross-sectional views showing a conventional method of fabricating a dual damascene structure. A dual-damascene technique is a technique that forms a metallic interconnection
114
(
FIG. 1B
) in a dielectric layer
106
. In
FIG. 1A
, a dielectric layer
106
is first formed over a substrate
100
, and then the dielectric layer
106
is planarized. According to the required design, the dielectric layer
106
is then patterned. A trench
108
and a via hole
110
are formed to expose a portion of the conductive layer
102
. In
FIG. 1B
, a barrier layer
112
is formed over the substrate
100
. A copper layer
114
is formed over the substrate
100
to fill the trench
108
and the via hole
110
. A conductive line and a via contact are thus simultaneously formed.
The barrier layer
112
having a high stability is used to solve the above-described problems, such as copper atom diffusion and poor adhesion between the copper layer
114
and the dielectric layer
106
. As shown in
FIG. 1C
, a chemical-mechanical polishing (CMP) step is performed. Because it is difficult to etch the copper layer
114
, the conventional method solves this difficulty by using the CMP step instead of performing an etching step. Thus, the difficulty in etching the copper layer
114
does not occur.
Typically, the material of the barrier layer
112
in the dual damascene structure is tantalum/tantalum nitride (Ta/TaN). Because it is difficult to remove the Ta/TaN layer by chemical-mechanical polishing, the dual damascene structure is still formed with difficulty. In order to remove the barrier layer
112
, it is necessary for the conventional method to perform an over-polishing step. Since the etching rate for the Ta/TaN barrier layer
112
is lower than that of the copper layer
114
, the copper layer
114
is easily dished or suffers from an erosion problem. Thus, the process is still not optimal.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a dual damascene structure. A dielectric layer is formed on a substrate. A diffusion barrier layer is formed on the dielectric layer. A portion of the diffusion barrier layer and the dielectric layer is removed to form a trench and a via hole. A barrier layer is formed on the diffusion barrier layer and in the trench and the via bole. The barrier layer on the diffusion barrier layer is removed by chemical-mechanical polishing. A conductive layer is formed in the trench and the via hole by selective deposition. A planarization step is performed with the diffusion barrier layer serving as a stop layer.
During the selective deposition of the conductive layer, the barrier layer serves as an activation center for selective deposition. The conductive layer easily fills the trench and the via hole. In contrast, since the diffusion barrier layer does not serve as an active center, it is difficult to deposit the conductive layer on the diffusion barrier layer. Thus, there is a high selectivity of the conductive layer between the barrier layer and the diffusion barrier layer.
The invention removes the barrier layer, which is on the diffusion barrier layer, before the step of forming the conductive layer in the trench and the via hole. The conductive layer is then formed by selective deposition. There is a high selectivity between the barrier layer, which is in the trench and the via hole, and the diffusion barrier layer. Thus, the conductive layer is deposited almost only in the trench and the via hole. Therefore, the undesired conductive layer on the diffusion barrier layer can be easily removed by chemical-mechanical polishing, so as to prevent the occurrence of a dishing effect and a erosion problem of the conductive layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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