Method of fabricating dual damascene

Details Method of fabricating dual damascene Method of fabricating dual damascene

1999-05-10

2000-01-25

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438628, 438634, 438644, 438633, 438700, H01L 214763, H01L 21311

Patent

active

060178175

ABSTRACT:
A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.

REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 5604156 (1997-02-01), Chung et al.
patent: 5801094 (1998-09-01), Yew et al.
patent: 5891513 (1999-04-01), Dubin et al.

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