Method of fabricating dielectric layer in alignment marker area

Details Method of fabricating dielectric layer in alignment marker area Method of fabricating dielectric layer in alignment marker area

1999-02-16

2001-01-30

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

C438S758000

Reexamination Certificate

active

06180537

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87120715, filed Dec. 14, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming an alignment marker area.
2. Description of the Related Art
The purpose of a photolithographic process is to transfer a predetermined pattern onto a wafer. In order to transfer the predetermined pattern onto the wafer precisely, it is necessary to align the wafer before a photoresist exposure step takes place. In a wafer alignment procedure, trenches are first formed in specific areas of the wafer. The trenches are used to define an alignment marker area. The wafer alignment is obtained by detecting the reflection lights from the trenches in the alignment marker area.
FIGS. 1A through 1B
are schematic, cross-sectional views of a conventional method of forming a dielectric layer in an alignment marker area.
In
FIG. 1A
, a wafer
100
having an alignment marker area
102
and a device area
104
is provided. The alignment marker area
102
includes trenches
102
a
and
102
b
formed in the wafer
100
. The depth of the trenches
102
a
and
102
b
is about 1200 Å. A device layer
106
, which includes a variety devices (not shown), such as a silicon substrate, a source/drain region, a gate, etc., is formed on the wafer
100
in the device area
104
.
In
FIG. 1B
, a metallic interconnection fabricating process is performed. A dielectric layer
108
is formed over the wafer
100
. Commonly, the dielectric layer
108
is sufficiently transparent in a photolithographic process. The transparency of the dielectric layer
108
is advantageous to the alignment detection for the wafer
100
. However, when the dielectric layer
108
is too thick, often thicker than 40000 Å, it is difficult to detect trenches
102
a
and
102
b
in the alignment marker area
102
.
SUMMARY OF THE INVENTION
A method of fabricating a dielectric layer in an alignment marker area. A wafer having an alignment marker area is provided. The alignment marker area has a plurality of large trenches and a plurality of small trenches. A dielectric layer is formed over the wafer. Portions of the dielectric layer in the alignment marker area are removed to form a plurality of trench structures. The trench structures in the dielectric layer are directly above the large trenches. A distance between the sidewalls of the trench structures and the sidewalls of the large trenches is greater than 0.5 mm.
The invention can also be used to form an alignment marker area on an edge of a wafer. A drainage structure, with an opening edge along the edge of the wafer, is also formed in the dielectric layer when the trench structures are formed. Thus, the slurry used in a chemical mechanical polishing step can drain off the edge of the wafer because of the drainage structure.
The invention can further provide a method for controlling a thickness of multiple dielectric layers in an alignment marker area. A wafer having an alignment marker area and a device area is provided. The alignment marker area comprises a plurality of large trenches and a plurality of small trenches. A dielectric layer over the wafer. A plurality of trench structures and a plurality of contact openings are formed in the dielectric layer. The trench structures are located above the large trenches. The contact openings are formed in the dielectric layer in the device area. A first metallic layer is formed on the dielectric layer to fill the contact openings. A portion of the first metallic layer and a portion of the dielectric layer are removed to form a plurality of metallic plugs in the contact openings. A second metallic layer is formed on the metallic plugs. An inter-metal dielectric layer is formed on the dielectric layer and the second metallic layer. A portion of the inter-metal dielectric layer is removed to make the inter-metal dielectric layer in the alignment marker area thinner than the inter-metal dielectric layer in the device area.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5401691 (1995-03-01), Caldwell
patent: 5786260 (1998-07-01), Jang et al.
patent: 5889335 (1999-03-01), Kuroi et al.
patent: 5958800 (1999-09-01), Yu et al.
patent: 6043133 (2000-03-01), Jang et al.

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