Method of fabricating crack resistant inter-layer dielectric...

Details Method of fabricating crack resistant inter-layer dielectric... Method of fabricating crack resistant inter-layer dielectric...

1998-09-10

2001-05-01

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S626000, C438S632000

Reexamination Certificate

active

06225209

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the lnvention:
This invention relates to a method of fabricating an inter-layer dielectric (ILD) for a salicide process, and more particularly, to a method of fabricating a crack resistant ILD for a salicide process.
2. Description of Related Art:
Because of semiconductor device line width and pattern downsizing, the conductivity of the polysilicon gate of a metal-oxide-semiconductor (MOS) device and the wiring line of a semiconductor device is lowered. A gate includes one or more metal or salicide layers formed on top of a polysilicon layer. Compared with a gate containing only polysilicon, the foregoing gate has a lower resistance. A salicide gate is fabricated by forming a salicide layer, such as a titanic silicide, with a thickness of about 1000Å, to cover a polysilicon layer, with a thickness of about 1000 to 3000Å, wherein the salicide layer provides a horizontal conducting path with a lower resistance above the gate.
Because the existence of an ILD layer is to prevent an electric short circuit between the gate and the metal layer, which is formed by a follow-up sputtering process, normally, a relatively thick insulating layer is formed on the gate, to be used as an ILD layer after the gate is formed, to insulate both the gate and the metal layer. After the formation of the ILD layer, the follow-up patterning process is performed to form the contact hole.
FIGS. 1A through 1C
are sectional views showing a conventional method of fabricating a crack resistant ILD for a salicide process. Referring to
FIG. 1A
, gate oxide
102
and polysilicon layers
104
a
and
104
b,
which are used as gates, are formed on the substrate
100
. Then, before the formation of spacer
106
, a light ion implantation is performed on the substrate
100
. After the spacers
106
are formed on the sides of the gate
104
a
and
104
b,
heavy ion implantation is performed on the substrate
100
to form lightly doped drain (LDD) regions
108
. A thermal process is performed to form a titanium layer on the substrate
100
. This titanium layer reacts with the substrate
100
and the polysilicon used as gates
104
a
and
104
b
, to form titanium silicide
110
a
and
110
b
on the lightly doped drain regions
108
, and gates
104
a
and
104
b.
A insulating layer
112
, such as a non-doped silicon oxide layer, is formed on the substrate
100
to cover the gates
104
a
and
104
b,
and the substrate
100
after the rest of the titanium layer is removed from the substrate
100
.
Referring to
FIG. 1B
, an ILD layer is formed on the substrate
100
, wherein the formation of the ILD layer includes first forming a borophosphosilicate glass (BPSG) layer
114
a
on the insulating layer
112
. This is followed by forming a spin-on glass (SOG) layer
114
b
on the BPSG layer
114
a,
and performing a chemical-mechanical polishing process. The SOG layer is used to fill the dish locations and holes on the surface of the BPSG layer to improve planarity. Then, a patterning process is performed form a contact hole
116
which is electrically connected to the lightly doped regions
108
.
Because natural oxide is formed on the bottom surface of the contact hole
116
, an extra process for removing the native oxide using chemical etching liquid is required before the metal sputtering process is carried out. However, the ILD layer
114
a
and insulating layer
112
are very easily damaged by the chemical etching liquid. Once the ILD layer
114
a
is damaged by the chemical etching liquid, the chemical etching liquid further damages the insulating layer
112
and the spacers
106
through the cracks
120
within the ILD layer
114
a.
As a result, the metal layer
118
, which fills the contact hole
116
in the follow-up fabrication process also fills the cracks
120
, creating bridges between gates
104
a
and
104
b,
which cause short circuits and abnormal currents.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabricating a denser ILD layer to prevent damage to the ILD layer caused by chemical etching liquid. This will in turn prohibit the formation of bridges between the polysilicon layers, and current leakage can be eliminated.
In accordance with the foregoing and other objectives of the present invention, the invention provides a method of fabricating a crack resistant—ILD for a salicide process. The method includes forming source/drain regions on the sides of a gate of a provided substrate, forming a salicide layer on the gate, and on the source/drain regions, and forming first an insulating layer and then a planarized ILD layer on the substrate. The ILD layer includes a BPSG layer and a SOG layer. A thermal process is then performed on the ILD layer to form a denser ILD layer, which is more resistant to undesired etching.


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