Method of fabricating copper damascene

Details Method of fabricating copper damascene Method of fabricating copper damascene

1999-08-10

2001-03-13

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S629000, C438S631000

Reexamination Certificate

active

06200890

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating multi-level metal interconnects for a semiconductor device. More particularly, the present invention relates to a method of fabricating a copper (Cu) damascene.
1. Description of Related Art
As the integration of the integrated circuit (IC) increases, the surface of the chip is unable to provide adequate area for fabricating the required interconnect. In order to satisfy the increased requirement for the interconnect after reducing the metal oxide semiconductor (MOS) transistor, metallization has gradually become the method employed for many IC devices. Each electrode of the MOS transistor and the metal layers are isolated from each other by a dielectric layer and connected by contact plugs, while the metal layers are also isolated from each other by the dielectric layers and connected by via plugs. However, a barrier layer is usually formed as a conducting material before plug formation to increase the adhesion between the contact plug and the electrode (or metal layer), while preventing a spike effect between the metal plugs and the silicon interface.
During a back end process of the semiconductor device, the current density of metal lines has gradually increased with the reduction of the width of metal lines. As a result, the conventional metal lines, made principally of aluminum (Al) may be influenced by electron migration (EM), which further reduces the reliability of the device.
To solve the problems where the semiconductor device mentioned above has entered the sub-quarter micron process, the use of copper (Cu) with a minimum EM has become the uniform choice for all semiconductor manufactures.
However, as Cu is not easily etched by using common etching gases, the manufacture of Cu conducting wires can no longer be achieved by conventional methods. A method of fabricating a Cu damascene is thus proposed as a solution for the above problem.
As the integration of the IC keeps increasing, it becomes increasingly difficult to manufacture a metal interconnect with better yield and reliability. The method for fabricating a double metal damascene is a method which first etches out a dielectric opening for the metal interconnect in the dielectric layer, and then fills the opening with metal as an interconnect. Such method can satisfy the need for high yield and reliability during the process, and thus it has become the best choice for manufacturing the sub-quarter micron interconnect.
FIG. 1
is a schematic diagram illustrating the manufacture of a Cu damascene in the prior art.
Referring to
FIG. 1
, a dielectric layer I
0
is formed, wherein the dielectric layer
10
is formed on a substrate (not shown). This dielectric layer
10
may be an inter-layer dielectric or an inter-metal dielectric layer (IMD layer). A plurality of openings
12
are formed in the dielectric layer
10
by photolithographic etching, while a barrier layer (not shown) is formed to conformally cover the openings
12
and the dielectric layer
10
. A Cu layer (not shown) is then formed to cover the barrier layer and to fill the openings
12
. A barrier layer
14
and Cu layer which cover the surface of the dielectric layer
10
are removed by chemical mechanical polishing (CMP), so that a plurality of Cu conducting wires
16
and the barrier layer
14
are formed to complete the manufacture of the Cu damascene structure. Consequently, the Cu damascene structure is covered by a dielectric layer
18
, which forms the resultant structure shown in FIG.
1
.
However, it has recently been discovered that a Cu EM may readily occurs between the Cu conducting wires
16
and the dielectric layer
18
. In addition, as both the barrier layer
14
and the Cu layer that cover the surface of the dielectric layer
10
are removed by CMP, the portion of the sidewall adjacent to the top of the barrier layer
14
may produce pinholes (not shown) due to the stress. This may lead to current leakage on the sidewall of the barrier layer
14
(shown as dash lines along the interface
19
in FIG.
1
), thus reducing the reliability of the device.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a Cu damascene, which prevents not only electron migration (EM), but also occurrence of the current leakage on the sidewall of the barrier layer, whereby the reliability of the device is improved.
The invention provides a fabricating method for a Cu damascene; the method includes forming a dielectric layer, in which a plurality of openings are formed. A barrier layer is formed conformal to the profile of the openings so as to form a plurality of Cu conducting wires in the openings. A part of the dielectric layer is removed by etching until the Cu conducting wires project out the surface of the dielectric layer to expose a part of the sidewall of the barrier layer. A top barrier layer is formed to conformally cover the surface of the dielectric layer, the sidewall of the barrier layer, and the surface of the Cu conducting wires. Next, an oxide layer is formed on the top barrier layer by plasma enhanced chemical vapor deposition (PECVD). This PECVD oxide layer has poorer step coverage on the dielectric layer
20
between two Cu lines. An etching back is performed to remove a part of the oxide layer so as to expose a part of the top barrier layer located between the Cu conducting wires. With the remaining oxide layer serving as an etching mask and the dielectric layer as an etching stop layer, the exposed part of the top barrier layer is removed to expose the surface of the dielectric layer.
According to the invention, a part of the dielectric layer is removed to allow the projection of the Cu conducting wires from the surface of the dielectric layer while exposing a part of the sidewall of the barrier layer. A top barrier layer is formed to contain Cu in the Cu conducting wire so as to prevent the Cu EM, while the top barrier layer can also compensate the initial barrier layer that was damaged. Thus, the leakage current between two Cu conducting wires is prevented.
The purpose of the invention is to prevent the Cu EM and the current leakage from the sidewall of the barrier layer, so that the device can maintain better reliability.
According to the invention, an oxide layer with a uniform thickness is deposited by PECVD. An etching back is performed to remove a part of the oxide layer until a part of the top barrier layer located between the Cu conducting wires is exposed. With the remaining oxide layer serving as an etching mask and the dielectric layer as an etching stop layer, the exposed part of the top barrier layer is removed to expose the surface of the dielectric layer. An additional and precise mask is not required in this case, while the process window may also be increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6054378 (2000-04-01), Skala et al.
patent: 6066559 (2000-06-01), Gonzalez et al.
Microstructure and Electromigration in Copper Damascene Lines, IEEE Mar. 1999.
Surface Electromigration in Copper Interconnects, Dept. of Electrical and Electronic Engineering, Queen's University, Belfast, U.K., IEEE Mar. 1999.
Leakage Current Degradation and Carrier Conduction Mechanisms For Cu/BCB Damascene Process Under Bias-Temperature Stress, IEEE Mar. 1999.

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