Fishing – trapping – and vermin destroying
Patent
1992-10-13
1993-08-03
Quach, T. N.
Fishing, trapping, and vermin destroying
437 89, 437160, 437184, 148DIG110, H01L 21283, H01L 21225
Patent
active
052328732
ABSTRACT:
A semiconductor device substrate has a major surface on which is located an insulating layer, such as silicon dioxide, having an aperture penetrating through it all the way down to the major surface. An impurity-doped plug, such as tungsten doped with zinc, is spatially selectively deposited in the aperture to a thickness such that the height of the plug is significantly less than the height of the aperture in the insulating layer, by means of a rapid-thermal-cycle low-pressure-metalorganic-chemical vapor deposition (RTC-LP-MOCVD) process. Then another plug, of (pure) conductive barrier metal such as tungsten, is deposited on at least the entire top surface of the impurity-doped plug and on the sidewalls of the insulating layer. The structure being fabricated can then be heated, in order to diffuse the impurity into the underlying semiconductor device substrate. A metallization layer such as titanium/platinum/gold can be deposited on the (pure) conductive barrier metal and patterned, in order to supply a desired access metallization for the device.
REFERENCES:
patent: 3887993 (1975-06-01), Okada et al.
patent: 4843033 (1989-06-01), Plumton et al.
patent: 5071798 (1991-12-01), Nakata
patent: 5086016 (1992-02-01), Brodsky et al.
patent: 5089438 (1992-02-01), Katz
patent: 5141897 (1992-08-01), Manocha et al.
patent: 5158896 (1992-10-01), Burroughes et al.
Tiwari, S. et al. "Heterostructure Devices Using Self-Aligned p-Type Diffused Ohmic Contacts," IEEE Electron Device Letters, vol. 9, No. 8, Aug. 1988, pp. 422-424.
Tiwari, S. et al., "Lateral Ga.sub.0.47 In.sub.0.53 As and GaAs p-i-n Photodetectors by Self-Aligned Diffusion," IEEE Photonics Technology Letters, vol. 4, No. 4, pp. 396-398.
Katz, A. et al., "Rapid Thermo Chemical Vapor Deposition of Silicon Dioxide Films onto InP", Applied Physics Letters, vol. 59, pp. 579-581 (1991).
Geva Michael
Katz Avishay
AT&T Bell Laboratories
Caplan D. I.
Quach T. N.
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