Method of fabricating chip scale package

Details Method of fabricating chip scale package Method of fabricating chip scale package

2000-07-20

2001-09-11

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C438S014000, C324S755090, C324S757020, C324S760020

Reexamination Certificate

active

06287878

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor package, and more particularly, to a chip scale package (CSP) fabrication method including an electric die sort (EDS) and a burn-in test.
2. Description of the Related Art
Semiconductor packages have been continuously improved to meet new demands for high-performance, small-size and high-speed electronic appliances. Accordingly, semiconductor packages have been evolved from old-fashioned dual in-line packages (DIPs) to state-of-the-art semiconductor packages such as CSPs. As a result, electronic appliances such as camcorders or portable telephones can be miniaturized using the CSPs as their essential components.
The CSPs are known to be ideal for a package having 100 pins or more with high speed operation, or for a package having a large size chip. Although the definition of the CSPs has not been fixed in semiconductor industry, the packages that are smaller than 120% of the size of a semiconductor chip is typically referred to as a CSP. Even semiconductor packages larger than 120% of the size of a chip, such as ball grid array (BGA) packages, land grid array (LGA) packages, and small outline non-leaded (SON) packages, are considered as a CSP. In particular, the BGA packages having solder balls instead of leads mounted on the lower surface thereof, the LGA packages having a land array mounted on the lower surface thereof, and the SON packages having two land arrays instead of leads mounted on the lower surface thereof are examples of the CSPs.
FIG. 1
is a flowchart illustrating a typical process for fabricating CSPs. Referring to
FIG. 1
, a plurality of semiconductor chips are formed on a wafer by integrated circuit fabricating processes. Then, the plurality of chips on the wafer are tested to identify good dies from bad dies depending on electrical characteristics or functionality of each chip by performing an electric die sorting (EDS) process. The EDS process utilizes a probe card having probe needles mounted thereon for electrically connecting a tester to an individual chip for testing, in step
51
. Following the EDS process, preferably, only good dies are packaged into a CSP strip, in step
53
. Next, the CSP strip is singulated (separated) into individual CSPs, in step
55
.
The individual CSPs are subjected to a burn-in test for inducing the failure of marginal CSPs with defects, in step
57
. This burn-in test accelerates failure mechanisms such that devices which have the potential to fail later but which failure would not otherwise be apparent at nominal test conditions can be eliminated by applying a serious stress, for example, heat, voltage or high frequency such as a clock, to a semiconductor package. Thus, defective CSPs can be screened out early before a final test, and only non-defective CSPs are subjected to the final test, in step
59
.
Next, the final test is preformed, in step
59
, on CSPs that are determined to be good (non-defective) in the burn-in test. Then, CSPs determined to be good (fully-funictional) by the final test are marked their corresponding product titles, in step
61
. Also, in step
61
, the CSPs are finally inspected for visual defects. Thereafter, good CSPs are surface-mounted on a module board, in step
63
. The CSP module is subjected to a module test, in step
65
, and finally packed to be sent to end users, in step
67
. Here, reference numeral
69
denotes a section where process steps are being carried out with singulated CSPs, before module assembly. Reference numeral
71
denotes a section from module assembly to final packing, where process steps are being carried out with a CSP module board.
FIG. 2
is a schematic view illustrating a final test using a plastic tray
93
that is generally used to transport CSPs. Referring to
FIG. 2
, singulated CSPs are placed on the plastic tray
93
and then are transported between the processes using the tray
93
. Thus, in the final test, singulated CSPs are contained on the test tray
93
. The test tray
93
has a plastic main body
89
whose surface is treated as anti-static, and grooved pockets
91
on which singulated individual CSPs
81
are placed. Thereafter, the singulated CSPs placed on the test tray
93
are loaded onto a handler connected to a tester. In the handler, solder balls acting as external connection terminals for CSPs
81
are connected to socket contact terminals
87
(e.g., POGO pins) in a socket
85
on an interface board
83
, and the CSP
81
is subjected to the final test. Although not shown, in burn-in test equipment, CSPs are inserted into sockets on a burn-in board, and subjected to a reliability test to sort out defective CSPs early.
According to this conventional CSP fabrication method, singulated individual CSPs are loaded on a plastic tray and unloaded from a burn-in board numerous times during a burn-in-test. Also, in a final test, loading and unloading to and from the plastic tray are repeated.
Hence, the final test and the burn-in test with respect to singulated individual CSPs have the following problems.
First, as external connection terminals, CSPs generally use solder balls, rather than outer leads. Such solder balls could be easily damaged by outside impact or physical stress. Further, encapsulating materials for the CSPs are relatively weaker than that of conventional encapsulating materials for ceramic or plastic packages. Thus, generally the CSPs are vulnerable against physical impact during the repeated loading and unloading in the burn-in test and the final test. Accordingly, various visual defects can occur easily. The visual defects include package breaking, cracking, damage to solder balls, and consequential contact failure. These visual defects significantly reduce the yield of the CSP fabrication process.
Second, the CSPs being a surface-mounting semiconductor package have more contact terminals than the other conventional semiconductor packages. Thus contact failure in the CSPs is more and more frequent due to an increase in the number of contact terminals during the burn-in test and the final test.
Third, a complicated mechanism is needed to connect the socket to solder balls of the CSPs. This inevitably increases the price of socket, in tun, increasing overall manufacturing costs.
Fourth, the burn-in testing process and the final test require a great amount of time and man-power for repeated loading and unloading. Accordingly, an excessive amount of time and man-power is required in the conventional CSP fabrication process, thus lowering productivity.
Accordingly, what is needed is a better way to fabricate the CSPs minimizing the visual defects, contact failure and the other problems discussed above, thereby improving productivity and lowering manufacturing costs.
SUMMARY OF THE INVENTION
The above-mentioned problems with fabricating CSPs are addressed by the present invention and which will be understood by reading and studying the followings specification.
In the present invention chip scale package (CSP) fabrication method, CSPs are assembled into a CSP strip. Then, the CSP strip is directly subjected to a final electrical test without performing a CSP strip singulation process. Accordingly, a burn-in test is performed on the CSP strip (module board) rather than on an singulated individual CSPs, so that the external impact applied to CSPs can be minimized and the probability in which contact failure occurs is reduced. Further productivity is improved by saving time and man-power required for loading and unloading, and the manufacturing costs can be reduced by avoiding use of an expensive socket for singulated CSPs.
Another feature of the present invention is that a final test process is performed on a CSP strip in the CSP fabrication process.
Still another feature of the present invention is to provide a CSP burn-in testing method for burn-in testing CSPs assembled on a module board.
To achieve the first feature, the present invention provides a chip scale package (CSP) fabrication method including: (a

Affiliated with

Also associated with

Rating

Method of fabricating chip scale package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating chip scale package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating chip scale package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2497096