Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2006-09-11
2008-11-11
Soward, Ida M (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S374000, C257S501000, C257S510000, C257S524000, C257S905000
Reexamination Certificate
active
07449763
ABSTRACT:
This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.
REFERENCES:
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 5208179 (1993-05-01), Okazawa
patent: 5268320 (1993-12-01), Holler et al.
patent: 5278438 (1994-01-01), Kim et al.
patent: 5843820 (1998-12-01), Lu
patent: 5886368 (1999-03-01), Forbes et al.
patent: 5998264 (1999-12-01), Wu
patent: 6034393 (2000-03-01), Sakamoto et al.
patent: 6171909 (2001-01-01), Ding et al.
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6235589 (2001-05-01), Meguro
patent: 6441421 (2002-08-01), Clevenger et al.
patent: 6444592 (2002-09-01), Ballantine et al.
patent: 6548374 (2003-04-01), Chung
patent: 6586804 (2003-07-01), Choi et al.
patent: 6720610 (2004-04-01), Iguchi et al.
patent: 6803272 (2004-10-01), Halliyal et al.
patent: 6855591 (2005-02-01), Kim
patent: 6921947 (2005-07-01), Furuta et al.
patent: 6927447 (2005-08-01), Choi et al.
patent: 7038291 (2006-05-01), Goda et al.
patent: 7388249 (2008-06-01), Lee
patent: 2003/0020119 (2003-01-01), Arai et al.
patent: 2003/0227042 (2003-12-01), Hibi et al.
patent: 8-172174 (1996-07-01), None
patent: 2001-006386 (2001-07-01), None
English language abstract of Japanese Publication No. 8-172174.
English language abstract of Korean Publication No. 2001-006386.
O'Connor, Kevin J., et al., “A Novel CMOS Compatible Stacked Floating Gate Device Using Tin as a Control Gate,” Jan. 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 61-62.
Momiyama, Youichi, et al., “Ultra-Thin TA2O5/SIO2Gate Insulator With Tin Gate Technology for 0.1 μm MOSFETS,” Jan. 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 135-136.
Choi Jeong-Hyuk
Hur Sung-Hoi
Lee Chang-Hyun
Park Kyu-Charn
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Soward Ida M
LandOfFree
Method of fabricating cell of nonvolatile memory device with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating cell of nonvolatile memory device with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating cell of nonvolatile memory device with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4038624