Method of fabricating buried contact

Details Method of fabricating buried contact Method of fabricating buried contact

2000-12-01

2002-06-18

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000

Reexamination Certificate

active

06406985

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89124131, filed Nov. 15, 2000.
BACKGROUND OF THE INTENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a buried contact. More particularly, this invention relates to a method of fabricating a buried contact without formation of a micro-trench even when a misalignment occurs.
2. Description of the Related Art
To establish the contact between a drain region of a load device and other n-channel devices, a buried contact is often used to connect a diffusion region in a substrate and a polysilicon line.
FIGS. 1A
to
1
C show a conventional method for fabricating such buried contact.
In
FIG. 1A
, on a substrate
100
having a shallow trench isolation
102
, a gate oxide layer
104
and a polysilicon layer
106
are sequentially formed. A mask layer
108
with opening exposing a portion of the polysilicon layer
106
, under which a buried contact is to be formed, is formed on the polysilicon layer
106
.
In
FIG. 1B
, the exposed polysilicon layer
106
and the underlying portion of the gate oxide layer
104
are removed expose portion of the substrate
100
. A diffusion region
110
is then formed in the exposed substrate
100
. The mask layer
108
is removed to expose the polysilicon layer
106
. Another polysilicon layer
112
is further formed on the exposed substrate
100
and the exposed polysilicon layer
106
. A photoresist layer
114
to pattern a gate is then formed on the polysilicon layer
112
. Ideally, the coverage of the photoresist layer
114
includes the polysilicon layer
112
aligned over the diffusion region
110
.
In
FIG. 1C
, using the photoresist layer
114
as a mask, the exposed polysilicon layer
112
and the polysilicon layer
106
underlying the exposed polysilicon layer
112
are removed until the substrate
100
is exposed to form the gate. Being protected by the photoresist layer
114
, the polysilicon layer
112
aligned over the diffusion region
100
is not removed. However, when an alignment offset occurs between the photoresist layer
108
and the photoresist layer
114
, the photoresist layer
114
is not exactly aligned all over the diffusion region
110
, a portion of the polysilicon layer
112
over the diffusion region
110
is exposed. During the step of patterning the gate, as the substrate
100
comprises a gate oxide layer
104
thereon an etching buffer, the substrate
100
is not damaged or etched away. However, the diffusion region
110
does not have a gate oxide layer
104
, so that the diffusion region
110
is subject to the etching environment of the polysilicon layers
112
and
106
. The diffusion region
110
is thus very easily damaged to form a micro-trench
116
as shown in FIG.
1
C.
Therefore, in the conventional fabrication process, one a misalignment or an alignment offset occurs, a mirco-trench is easily formed in the buried contact to cause a disconnect between the polysilicon layer
112
and the diffusion region, and to seriously affect the performance of devices.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a buried contact. On a substrate having a shallow trench isolation thereon, a gate oxide layer and a polysilicon layer are sequentially formed. The polysilicon layer and the gate oxide layer are patterned to expose a portion of the substrate. A diffusion region is formed in the exposed substrate. On the polysilicon layer and the exposed diffusion region, an amorphous silicon layer is formed. Consequently, a native oxide layer is formed between the polysilicon layer and the amorphous silicon layer, and between the amorphous silicon layer and the diffusion region. An anti-reflection coating layer is formed on the amorphous silicon layer. Using the native oxide layer as an etching buffer, the anti-reflection coating layer and the amorphous silicon layer are patterned until the diffusion region and the polysilicon layer are exposed. A spacer is formed on a sidewall of the patterned anti-reflection coating layer and the patterned amorphous silicon layer, while the exposed diffusion region is also covered thereby. Using the spacer and the patterned anti-reflection coating layer as a mask, the polysilicon layer and the gate oxide layer are etched until the substrate is exposed. A source/drain region is further formed in the exposed substrate.
In the method mentioned above, the first conductive layer (the polysilicon layer) and the second conductive layer (the amorphous layer) are removed in two different etching steps. While etching the etching conductive layer, that is, the amorphous silicon layer, the native oxide formed on the diffusion region and the polysilicon layer function as an etching buffer, so as to protect the underlying polysilicon layer and the diffusion region. While performing another etching step to remove the polysilicon layer to form the gate, the substrate is protected by the gate oxide layer, while the diffusion region is covered with a portion of the spacer. Again, the substrate and the diffusion regions are not damaged during the etching step. Therefore, the micro-trench formed in the conventional method is avoided in the invention, and the device performance can be maintained as required.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5053349 (1991-10-01), Matsuoka
patent: 5641708 (1997-06-01), Sardella et al.
patent: 5972759 (1999-10-01), Liaw
patent: 6001681 (1999-12-01), Liu et al.
patent: 6146981 (2000-11-01), Chen
patent: 6180500 (2001-01-01), Violette et al.

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