Method of fabricating bit line and bit line contact plug of...

Details Method of fabricating bit line and bit line contact plug of... Method of fabricating bit line and bit line contact plug of...

2001-08-24

2004-01-20

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S675000, C438S702000

Reexamination Certificate

active

06680254

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a bit line and contact plug for a dynamic random access memory (DRAM) cell, and more particularly to the fabrication of a bit line and a bit line contact plug for the DRAM cell.
2. Description of the Prior Art
A DRAM cell comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor that are built in a semiconductor silicon substrate. There is an electrical contact between the drain of a MOSFET and the bottom storage electrodes of the adjacent capacitor, forming a memory cell of the DRAM device. A large number of memory cells make up the cell arrays, which combine with the peripheral circuit to produce DRAMs.
In recent years, the dimensions of the MOSFETs have continuously shrunk so that the packing densities of these DRAM devices have increased considerably; thus, the dimensions of the MOSFETs and capacitors have become smaller; the line width of word lines, bit lines, and metal lines have become narrower; the distance between two bit lines, word lines or metal lines have also become closer. Since bit line contact plug connects bit line and drain region, and the bit line is on the top of the bit line contact plug. In conventional processes, formation of the bit line contact plug usually takes place before that of the bit line. The conventional processes for fabrication of the bit line and the bit line contract plug follow.
Referring to
FIG. 1A
, in this figure, bit lines
160
, word lines
102
, active areas
104
, source/drain region
112
, and bit line contact plug
142
are shown on the layout of the memory cell array of a DRAM cell.
FIG. 1B
is a sectional view along the A—A line of FIG.
1
A. In conventional processes, a semiconductor substrate
100
is provided, using a LOCOS Oxidation process to form a field insulating layer (not shown) on the substrate
100
. The field insulating layer isolates each Active Area. Thereafter, ordinary semiconductor processes, such as deposition, photolithography and ion implantation are used to form the transistor (not shown). The transistor is composed of a gate (not shown) and diffusion areas, such as the source/drain region
112
. Then, a first insulating layer
120
, which is made of borophosphosilicate glass (identified as BPSG hereafter), is formed to isolate the gate.
Referring to
FIG. 1C
, a photoresist layer
130
is formed on the first insulating layer
120
. After the photoresist layer
130
is defined, the first insulating layer
120
is defined to form a bit line contact window
140
, which exposes the surface of the source/drain region
112
.
Referring to
FIG. 1D
, a first conductive layer (not shown) is deposited to fill up the bit line contact window
140
. Then, a bit line contact plug
142
is formed, which electrically connects the source/drain region
112
.
Referring to
FIG. 1E
, by photolithography and etching, the top portion of the bit line contact plug
142
is defined to form a trench
150
.
Referring to
FIG. 1F
, a bit line
160
is formed by depositing a second conductive layer (not shown) to fill up the trench
150
. The bit line
160
electrically connects the source/drain region
112
through the bit line contact plug
142
. Manufacture of the bit line and the bit line contact plug of a memory cell is then completed.
Since memory devices have become highly integrated, the line width of a memory cell has been reduced to less than 0.08 micrometer. For conductive structures, however, the narrowed line width increases electrical resistance, and thus, increases the loss of current and heat generated by the device, and decreases the efficiency of the device. Accordingly, to reduce the electrical resistance, the increased line width of a device is necessary. And hence, in order to reduce the electrical resistance between the bit line contact plug and the source/drain region or the bit line and the bit line contact, enlarging the diameter of the bit line contact plug is necessary. Note the processes of a 0.14-micrometer device as an example. The distance between two neighboring bit lines is also about 0.14 micrometer. In order to reduce the electrical resistance, the ideal diameter of the bit line contact plug is about 0.17 to 0.18 micrometer. Using the processes of a 0.11 micrometer device as another example, the distance between two neighboring bit lines is about 0.11 micrometer. The ideal diameter of the bit line contact plug is about 0.13 to 0.14 micrometer. The distance between two bit lines cannot be less than 0.11 micrometer. The diameter of the bit line contact plug is usually larger than the distance between two neighboring bit lines. If misalignment occurs during the formation of the bit lines, two neighboring bit lines may possibly encroach on two neighboring bit line contact plugs.
FIG. 1G
shows two neighboring bit line encroaching on two neighboring bit line contact plugs because of misalignment in photolithography. The juxtaposition can cause a short circuit, resulting in failure of the operation of a DRAM device.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method for fabricating the bit line and the bit line contact plug of a semiconductor memory device, especially to avoid a bit line encroaching on two neighboring bit line contact plugs, which can cause short circuit or failure of the DRAM device.
In order to achieve the above object, a method of fabricating a bit lines and a bit line contact plug according to an embodiment of the present invention is disclosed. A semiconductor substrate having a transistor, comprising at least one diffused region formed thereon and overlaid by a first insulating layer is provided. A first masking layer is formed on the first insulating layer. The first masking layer and the first insulating layer are defined to form a first trench, which is above the diffusion region. A second masking layer is formed to fill up the first trench. A hole is formed by removing a portion of the second masking layer, which is above the diffusion region. A bit line contact window is formed by removing a portion of the first insulating layer right beneath the hole until the surface of the diffusion region is exposed. A bit line contact plug is formed by forming a first conductive layer to fill the bit line contact window. The residual second masking layer is removed to form a second trench. Thereafter, the first masking layer is removed. A bit line is formed by forming a second conductive layer to fill the second trench, Thus, the fabrication of the bit line and the bit line contact plug of a memory cell is complete.


REFERENCES:
patent: 6165898 (2000-12-01), Jang et al.
patent: 6300235 (2001-10-01), Feldner et al.
patent: 6323118 (2001-11-01), Shih et al.

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