Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2000-12-08
2002-10-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S309000, C438S341000, C438S203000, C438S933000
Reexamination Certificate
active
06472288
ABSTRACT:
DESCRIPTION
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the formation of bipolar transistors in integrated circuits and, more particularly, to the formation of high-performance transistors having independently controllable properties developed by independently defined doping profiles on the same integrated circuit chip, possibly together with CMOS circuitry.
2. Description of the Prior Art
While CMOS (complementary metal-oxide-semiconductor) transistors have become the technology of choice in recent years for all but the most stringent performance requirements of integrated circuits, bipolar transistors provide some performance benefits not otherwise obtainable, particularly for high frequency signals, such as noise and low current gain. For this reason, techniques have been developed to form combinations of bipolar NPN and PNP transistors together with CMOS transistors on a single chip. This technology is generally referred to as BICMOS.
However, at the current state of the art, the trend in integrated circuits is toward placing an entire system on a single chip because increases in integration density have allowed increases in performance (by reducing interconnect length and propagation time, improving isolation and eliminating on-chip and off-chip drivers) as well as in functionality and manufacturing economy. While BICMOS technology has allowed entire systems to be integrated on a chip for some applications, other applications have required high performance transistors to be placed on a separate chip that may be laminated with or otherwise connected to another chip, such as that described above. While such a structure allows avoidance of some of the necessary interconnection length, it is not an optimum solution for highest frequency performance.
Further, at the present state of the art, various RF microwave and high-speed wired logic networks have differing requirements for bipolar transistors that may be required in different functional blocks of the system. For example, emitter coupled logic (ECL) circuits require a high value of Ft (the frequency at which current gain of the transistor becomes unity, typically 40-120 GHz for high performance designs) and Fmax (the maximum frequency at which the transistor can oscillate, typically 50-150 GHz for high performance designs) approximating the same value. Microwave blocks require a moderate Ft and Fmax=1.5-2.0 Ft. Additionally, parameters such as current gain, base resistance and collector capacitance must be optimized quite differently depending on the function required in different blocks of the system. For example, a microwave heterojunction bipolar transistor (HBT) may have a pinched base resistance of Rdb=2,000-3,000 ohms/sq. while a digital transistor may have an Rdb=10,000 ohms/sq. or greater.
Such divergent values of transistor parameters have been very difficult and complicated if not impossible to obtain on a single chip. For example, in group III-V semiconductor compounds such as GaAs and AlGaAs, solutions such as completing one transistor, etching off all the films including emitter, base and any passivating layers, if required, in selected areas and forming a different transistor have been suggested. However, proposed processes are not BICMOS or silicon compatible. It is difficult to re-grow new layers in either group III-V transistors or silicon after reactive ion etching the surface, as was done in the prior art, because of the poor surface quality after etching. Additionally, the total thickness of the layers grown is quite different causing difficulty in removal of the films and planarization for further high-resolution lithography.
Further, it is not possible to share the thermal budget for high performance HBTs which are very differently optimized since optimization generally requires critical adjustment or design realization of the dopant profile within the respective transistors as well as optimization of base dimensions. Seeking to obtain different dopant profiles in transistors on the same chip has resulted in compromises that degrade performance and yield of one or more of the transistor types since independence of transistor design was not possible. For example, known processes may have required identical emitter depths, resulting in non-optimal capacitance, linearity and/or current gain, which are critical for analog and microwave applications.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a technique of providing completely independent optimization of bipolar transistors formed on the same chip.
It is another object of the present invention to provide a technique and structure for formation of bipolar transistors of potentially radically different electrical properties on the same chip with BICMOS circuits and compatible with silicon technologies.
In order to accomplish these and other objects of the invention, an integrated circuit and method for making the same is provided comprising the steps of protecting a silicon substrate with a protective layer selectively etchable to silicon, opening the protective layer at selected locations without etching the silicon substrate to form an opening, epitaxially growing a base layer over the opening in the protective layer, and repeating the steps of opening the protective layer and epitaxially growing a base layer at different locations and using materials having different material concentration profiles.
In accordance with another aspect of the invention, an integrated circuit device is provided having silicon collector regions and at least first and second transistors formed in combination with respective silicon collector regions, the transistors differing from each other by base width, size or material concentration profile.
In accordance with a further aspect of the invention, a method of forming transistors of different designs on a single chip is provided including steps of forming a first protective layer on a substrate including collector regions of respective transistors, forming a second protective layer on the first protective layer wherein the second protective layer and the first protective layer are selectively etchable with respect to each other, patterning the second protective layer and the first protective layer to a collector region, forming a first base layer, patterning the first base layer and the second protective layer to the first protective layer with a hard mask, forming a further second protective layer, patterning the further second protective layer and the first protective layer to another collector region, forming a second base layer, patterning the second base layer and the further second protective base layer to the first protective layer, and completing transistors including the first base layer and the second base layer, respectively.
REFERENCES:
patent: 5930635 (1999-07-01), Bashir et al.
Freeman Gregory G.
Schonenberg K. T.
Stein Kenneth J.
Subbanna Seshadri
Anya Igwe W.
Smith Matthew
LandOfFree
Method of fabricating bipolar transistors with independent... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating bipolar transistors with independent..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating bipolar transistors with independent... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2998566