Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2003-05-30
2004-12-14
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S126000, C257S787000, C257S778000
Reexamination Certificate
active
06830957
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of fabricating Ball Grid Array (BGA) packages, and more particularly, to a method of fabricating Flip-Chip BGA (FCBGA) packages using Build-Up (BU) substrates for carrying semiconductor chips thereon.
2. Description of Related Art
BGA (Ball Grid Array) is an advanced type of integrated circuit packaging technology which is characterized by the use of a substrate whose front side is mounted with a semiconductor chip and whose back side is mounted with a grid array of solder balls. After SMT (Surface Mount Technology) processing, the BGA package can be mechanically bonded and electrically coupled to a printed circuit board (PCB) by means of these solder balls.
FCBGA (Flip-Chip Ball Grid Array) is a more advanced type of BGA technology which is characterized by that the semiconductor chip is mounted in an upside-down manner over the substrate and bonded to the same by means of a plurality of solder bumps attached to the I/O (input/output) pads thereon. This feature allows the semiconductor chip to be electrically connected to the substrate without having to use bonding wires, thereby making the packages more compact in size and providing more I/O connections between the semiconductor chip and the substrate for carrying the same than conventional non-Flip-Chip type BGA packages.
FCBGA packages typically utilize a BU (Build-Up) substrate as chip carrier. However, the yield of BU substrates is generally poor as the fabrication of BU substrates requires complicate processes and technologies. As a result, the BU substrates are commercially available usually in the singulated form instead of a strip type of interconnected conventional BGA substrates, such that an encapsulation body for encapsulating the flip chip requires a molding or encapsulation process to be performed on one single BU substrate at one time. Related prior arts include, for example, U.S. Pat. No. 6,038,136 “CHIP PACKAGE WITH MOLDED UNDERFILL”; U.S. Pat. No. 5,918,746 “CARRIER FRAME USED FOR CIRCUIT BOARDS”; U.S. Pat. No. 5,200,366 “SEMICONDUCTOR DEVICE, ITS FABRICATION METHOD AND MOLDING APPARATUS USED THEREFOR”; to name just a few.
U.S. Pat. No. 6,038,136 teaches a molding process performed for a single BU substrate to form an encapsulation body that encapsulates a flip chip mounted on the substrate. This BU substrate is formed with an injection gate (usually made of gold) thereon through which an encapsulating resin (such as epoxy resin, etc.) can be injected to form the intended encapsulation body. However, since the I/O pads on the flip chip and corresponding conductive traces on the substrate are both arranged in high density, the provision of injection gate on the substrate would adversely affect or undesirably restrict the circuit and trace routability on the substrate.
Moreover, U.S. Pat. No. 6,038,136 further teaches the provision of a hole at the center of the substrate to serve as an air outlet during the molding process to drain air out of the mold, such that no void is left in the resulted encapsulation body and the concern of popcorn effect can be eliminated. However, formation of the hole or air outlet not only increases the fabrication cost of the substrate but further restricts the trace routability on the substrate.
U.S. Pat. No. 5,200,366 discloses the use of a three-piece type of mold for performing the molding process on a single BU substrate. When this mold composed of three pieces is in use during molding, a bottom piece of mold is placed underneath the substrate, while the other two top pieces of mold are mounted on the substrate in a manner that a gap is left between these two pieces and above the substrate to serve as an injection gate where the encapsulation compound can be injected to form the encapsulation body that encapsulates the flip chip on the substrate. However, one significant drawback to this technology is that the three-piece type of mold is rather complex in structure and thus expensively made, thereby undesirably increasing the overall fabrication cost of the FCBGA packages.
In addition, since all of the above-mentioned U.S. patents are primarily used to fabricate one single package unit on each single substrate or to perform the molding process on one single substrate at one time, they are complex and cost-ineffective to implement in practice and also fairly low in productivity of the fabricated packages. Therefore, it is greatly desired to provide a package fabrication method that is cost-effective to perform in a batch manner and allows high yield of fabricated FCBGA packages using the BU substrates.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of fabricating BGA packages, which can be used fabricate a batch of package units on one single substrate for the purpose of increase the throughput of fabrication.
It is another objective of the present invention to provide a method of fabricating BGA packages, which can be implemented without providing injection gate in the substrate so as not to restrict the circuit and trace routability on the substrate.
It is still another objective of the present invention to provide a method of fabricating BGA packages, which can be implemented without utilizing the costly three-piece type of mold to allow the fabrication more cost-effective to implement.
It is yet another objective of the present invention to provide a method of fabricating BGA packages, which can be implemented without having to provide an air outlet in the substrate but nevertheless allow the resulted encapsulation body to be free of voids to help assure the quality of the finished packages.
In accordance with the above and other objectives, the method of fabricating BGA packages proposed by the present invention comprises the steps of: preparing a batch of BGA substrates, each of the substrates having a front side and a back side, with a singulation line being predefined and at least one semiconductor chip being mounted on the front side of each of the substrates; preparing a carrier, which is formed with a series of cavities in communication with an injection gate; embedding the substrates respectively into the cavities of the carrier; performing an encapsulation process to form an encapsulation body to encapsulate each of the substrates and the corresponding one of the chips which is mounted on the substrate; performing a ball-implantation process to form a ball grid array over the back side of each of the substrates; and performing a singulation process to cut through the singulation lines on the substrates and thereby obtain a plurality of the BGA packages.
The BGA fabrication method according to the invention is characterized by the utilization of a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. Compared to prior art, since the invention provides an injection gate in the carrier, it would not restrict the circuit and trace routability on the substrate. Moreover, it allows the use of a two-piece type of mold for batch molding of a number of encapsulation bodies at the same time, allowing the fabrication to be more productive and cost-effective. Still moreover, the invention an be implemented without having to provide an air outlet in the substrate but nevertheless allow the resulted encapsulation body to be free of voids to help assure the quality of the finished packages. The invention is therefore more advantageous to use than the prior art.
REFERENCES:
patent: 5200366 (1993-04-01), Yamada et al.
patent: 5918746 (1999-07-01), Tokita et al.
patent: 6038136 (2000-03-01), Weber
patent: 6752204 (2004-06-01), Dishongh et al.
patent: 2003/0205799 (2003-11-01), Yunus
Huang Chien-Ping
Huang Chih-Ming
Pu Han-Ping
Ishimaru Mikio
Lebentritt Michael S.
Siliconware Precision Industries Co. Ltd.
Smith Brad
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