Method of fabricating barrier layer in integrated circuit

Details Method of fabricating barrier layer in integrated circuit Method of fabricating barrier layer in integrated circuit

1999-01-08

2001-05-15

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S653000, C438S654000, C438S656000, C438S660000, C438S663000, C438S675000

Reexamination Certificate

active

06232226

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority benefit of Taiwan application Serial No. 87117115, filed Oct. 15, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a barrier layer in the integrated circuit.
2. Description of the Related Art
Metal materials such as aluminum and tungsten are often used in the metallization process of current integrated circuits. Aluminum is selected as a wiring line between devices due to its low resistivity. Tungsten has a higher resistivity than aluminum, but it can be formed by chemical vapor deposition with better step coverage and tungsten easily forms fluoride with high volatility, so that there is no problem with removing tungsten by etching. Therefore, tungsten is widely used in fabrication of metal plugs. However, adhesion between tungsten and other materials, such as silicon, is not very good. A barrier/glue layer is necessary between tungsten and other material to enhance the adhesion thereof.
Titaniunem nitride is frequently used for a barrier/glue layer in very large scale integrated (VLSI) process. The titanium nitride is formed by physical vapor deposition, such as, sputtering. The titanium nitride has high contact resistance with the silicon layer and since the titanium easily reacts with the silicon to form titanium silicide with low resistivity, a titanium layer is therefore formed between the titanium nitride and the silicon to create a good ohmic contact therebetween.
FIG. 1A-1B
are schematic, cross-sectional views illustrating fabrication of a barrier layer according to prior art. Referring to
FIG. 1A
, a substrate
100
having devices (not shown) fabricated thereon is provided and a dielectric layer
126
with a contact window
130
is formed on the substrate
100
. A clamp
106
clamps the fringe of the substrate
100
with a length L of about 3 mm. A metal titanium layer
102
, which is a clamped titanium layer, is formed on the dielectric layer
126
and the contact window
130
.
Referring to
FIG. 1B
, the clamp
106
is removed, and therefore a distance L between the edge of the clamped titanium layer
102
and the fringe of the substrate
100
is about 3 mm. A titanium nitride layer
104
is formed over the substrate
100
. Since there is no clamp to clamp the substrate
100
while forming the titanium nitride layer
104
, the formation of the titanium nitride layer
104
is a clampless titanium nitride layer (101 TiN) hereinafter, the formation of TiN is referred as a 101 TiN process. A rapid thermal process (RTP) is carried out and a portion of the clamped titanium layer
102
reacts with the substrate
100
to form titanium silicide
132
with low resistance. A barrier layer including a clamped titanium layer
102
and a clampless titanium nitride layer
104
is completed.
Referring to
FIG. 1C
, since the thermal expansion coefficient of the clamped titanium layer
102
is different from that of the clampless titanium nitride layer
104
which covers the edge of the clamped titanium layer
102
, some microcracks
120
are produced within the clampless titanium nitride layer
104
when the RTP is performed. The microcracks expand to the center of the wafer to expose the clamped titanium layer
102
and form cracks
120
a.
Moisture thus enters into the wafer with devices through the cracks
120
,
120
a.
Source gas WF
6
diffuses into the microcracks
120
,
120
a
and reacts with clamped titanium layer
102
to form solid TiF
x
during the fabrication of the tungsten plug
128
. The solid TiF
x
even fills the microcracks to cause abnormal conduction, leakage or shorts of device.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of fabricating a barrier layer of integrated circuit. The abnormal conduction, leakage or shorts of devices due to microcracks within the titanium nitride layer can be resolved.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating a barrier layer of integrated circuit. A clamped metal layer is formed on a substrate. A RTP is performed and a clampless titanium nitride layer is formed on the clamped metal layer.
To achieve one of the objects as described, a method of fabricating a barrier layer of the integrated circuit is provided. A substrate having a clamped metal layer is provided. A clampless titanium nitride layer is then fabricated when the atmosphere temperature is adjusted and a RTP is carried out.
To achieve another of the objects as described, a method of fabricating a barrier layer of the integrated circuit is provided. A clampless metal layer and a clampless metal nitride layer are successively formed on the substrate and a RTP is then performed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5998870 (1999-12-01), Lee et al.
patent: 5998871 (1999-12-01), Urabe
patent: 6110789 (2000-08-01), Rhodes et al.

Affiliated with

Also associated with

Rating

Method of fabricating barrier layer in integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating barrier layer in integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating barrier layer in integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2559366