Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-11
2001-11-20
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S656000, C438S643000, C438S648000
Reexamination Certificate
active
06319826
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a barrier layer.
2. Description of the Related Art
As the integration of integrated circuits increase, the surface area of a wafer becomes insufficient for fabrication of required interconnections. In order to meet the surface requirement of the interconnections, multi-layered interconnections have become widely used in highly integrated devices. Typically, a dielectric layer is formed between metallic layers to isolate the metallic layers from each other. A metallic plug is formed to connect the metallic layers to each other. However, in order to improve the adhesion between the metallic plug and other materials as well as to avoid a spike effect between the metallic plug and silicon material, it is necessary to form a barrier layer before the metallic plug.
Conventionally, physical vapor deposition (PVD) is used to form a barrier layer for a contact or a via with a small aspect ratio (A. R.). However, in a fabrication process with a linewidth of 0.25 micrometers, or below, the aspect ratio correspondingly increases. Therefore, the barrier layer formed by physical vapor deposition on a contact, or a via, having a high aspect ratio does not have a sufficient step coverage ability. Thus, chemical vapor deposition, which provides a good step coverage ability, has become widely used for forming the barrier layer.
Titanium nitride (TixNy) is a barrier layer material frequently used in Very Large Scale Integration (VLSI). In order to improve the ohmic contact between the metallic plug and the silicon material, titanium nitride is usually used with titanium. For example, titanium/titanium nitride (Ti/TiN) are used together as a barrier layer in order to reduce the work function at a junction as well as to prevent the occurrence of the spike effect and electrical migration. Apart from using the titanium nitride as a barrier layer, in a tungsten plug fabrication process, the titanium nitride also can be used as an etching stop during a tungsten etching back step.
In
FIG. 1A
, a metal oxide semiconductor (MOS) transistor
102
is formed on a substrate
100
. A patterned dielectric layer
104
is formed on the substrate
100
to cover the MOS transistor
102
. The patterned dielectric layer
104
comprises a contact opening
106
. The contact opening
106
exposes a portion of a source/drain region
108
in the substrate
100
.
In
FIG. 1B
, a titanium layer
110
is sputter-deposited on the dielectric layer
104
to cover the exposed source/drain region
108
. The titanium layer
110
is conformal to the contact opening
106
. The thickness of the titanium layer
104
is about 40 angstroms. In order to increase the deposition ability of the titanium layer
110
, a collimator (not shown) is placed between the substrate
100
and a metallic target (not shown) while forming the titanium layer
110
. A titanium nitride layer
112
is formed on the titanium layer
110
by chemical vapor deposition (CVD). The titanium nitride layer
112
is conformal to the contact opening
106
. The titanium layer
110
and the titanium nitride layer together form a barrier layer. The thickness of the titanium nitride layer
112
is about 300 angstroms.
In
FIG. 1C
, a rapid thermal process (RTP)
114
is performed on the titanium layer
110
and the titanium nitride layer
112
in an environment of a NH
3
gas. A titanium silicon (Ti
x
Si
y
) layer
115
is formed between the titanium layer
110
and the source/drain region
108
, so as to decrease the resistance between a tungsten plug formed subsequently (shown in
FIG. 1E
) and the source/drain region
108
.
In
FIG. 1D
, a tungsten layer
116
, which has a good thermal endurance and a good conductivity, is formed on the titanium nitride layer
112
to fill the contact opening
106
by chemical vapor deposition.
In
FIG. 1E
, a tungsten etching back step is performed with SF
6
gas and argon gas serving as a source gas. The titanium nitride
112
serves as an etching stop layer during the etching back step. The tungsten layer
116
is etched back to form a tungsten plug
116
a.
However, the titanium nitride layer
112
formed by chemical vapor deposition is incompact. Additionally, organic impurities easily remain within the titanium nitride layer
112
. The remaining organic impurities in the titanium nitride layer
112
easily react with the titanium layer
110
during the rapid thermal process. In this manner, the titanium layer
110
is over consumed, so that the resistance between the tungsten plug
116
a
and the source/drain region
108
can not effectively be reduced as expected. Furthermore, titanium nitride
112
easily reacts with the nitrogen gas, and thus further increases the resistance between the tungsten plug
116
a
and the source/drain region
108
.
To solve the above-described problem, the conventional method is to change the process order, so that the rapid thermal process
114
is performed before the formation of the titanium nitride layer
112
. Thus, the titanium layer
110
and the titanium nitride layer
112
cannot be formed in an in-situ manner. Hence, the fabrication cost and the fabrication time are greatly increased.
In addition, because the titanium nitride layer
112
is incompact, the dielectric layer
104
, such as an oxide layer, and the titanium layer
110
are easily over-etched during the tungsten etching back step. In order to avoid the over-etching problem, it is necessary to form a thick titanium nitride layer
112
. However, the thick titanium nitride layer
112
causes the resistance to increase and degrades the device performance, as well. Thus, it is desirable to use chemical-mechanical polishing (CMP) instead of a tungsten etching back step. However, because the cost of the chemical mechanical polishing is high, it is not suitable for an economic fabrication process.
SUMMARY OF THE INVENTION
The invention provides a method of forming a barrier layer. A dielectric layer is formed on a substrate. The dielectric layer comprises an opening exposing a portion of the substrate. A metallic layer is formed over the substrate by ionized metallization-plasma(IMP) deposition. A first metallic nitride layer is formed on the first metallic layer by chemical vapor deposition. The second metallic nitride layer is formed on the first metallic nitride layer by high-power plasma deposition. The metallic layer, the first metallic nitride layer, and the second metallic nitride layer are conformal to the opening and together form a barrier layer.
The barrier layer formed in the present invention can be utilized in a metallic plug, a via in interconnections, a contact for dynamic random memory (DRAM), electrostatic discharge (ESD) devices, input/output (I/O) port, etc.
In comparison with the conventional method, the invention forms a thicker first metallic layer by IMP deposition. When a rapid thermal process is performed, the first metallic layer is sufficient to form a silicide layer. The compact second metallic nitride layer is formed on the first metallic nitride layer. In the rapid thermal process, the second metallic nitride layer prevents the first metallic nitride layer from reacting with NH
3
gas. High-power plasma deposition is used to form the compact second metallic nitride layer that covers the metallic nitride layer, which is formed by CVD. Since the second metallic nitride layer is compact, the second metallic nitride layer prevents the dielectric layer from being over-etched.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5604140 (1997-02-01), Byun
patent: 5705442 (1998-01-01), Yen et al.
patent: 5712193 (1998-01-01), Hower et al.
patent: 5766830 (1998-07-01), Sumi et al.
patent: 5851912 (1998-12-01), Liaw et al.
patent: 6045666 (2000-04-01),
Chen Ming-Shing
Kuo Yung-Chieh
Bowers Charles
Huang Jiawei
J.C. Patents
Smoot Stephen W.
United Microelectronics Corp.
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