Method of fabricating an isolation region for semiconductor devi

Details Method of fabricating an isolation region for semiconductor devi Method of fabricating an isolation region for semiconductor devi

1997-06-11

1998-09-08

Fourson, George R.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438947, 438696, H01L 2176

Patent

active

058044922

ABSTRACT:
A method of forming an isolation region is provided. A silicon oxide layer (4) is formed on a wafer (2). A first silicon oxynitride (6) layer is formed on the silicon oxide layer, and a silicon nitride layer (8) is formed on the first silicon oxynitride layer. The silicon nitride layer and a portion of the silicon oxynitride layer are etched. A TEOS-oxide layer (10) is deposited on the first silicon oxynitride layer and on the silicon nitride layer. Sidewall spacers (12) are formed on the sidewalls of the silicon nitride layer. A second silicon oxynitride layer (14) is deposited on the silicon nitride layer, sidewall spacers, and the silicon oxide layer. A second silicon nitride layer (16) is deposited and formed on the second oxynitride layer. A sacrificial oxide layer (18) is deposited on the second silicon nitride layer. A portion of the sacrificial oxide layer is etched. The second silicon oxynitride layer and the second silicon nitride layer that are not covered by the oxide layer are removed by dry etching. The sidewall spacers are subsequently removed to create grooves (20) adjacent the first silicon nitride layer. A thermal oxidation process is performed to form isolation regions (22) adjacent the first silicon nitride layer and in the wafer, and the first silicon nitride layer, the second silicon nitride layer, and the second silicon oxynitride layer are removed.

REFERENCES:
patent: 5173444 (1992-12-01), Kawamura

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