Method of fabricating an integrated planar transistor

Metal treatment – Compositions – Heat treating

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29576B, 148187, 357 34, 357 91, H01L 744, H01L 21265

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active

044564880

ABSTRACT:
A method is disclosed for fabricating a monolithic integrated planar transistor whose emitter region (1) is diffused into the base region (3) on one surface side of a semiconductor wafer (2), which base region is diffused into the collector region (4). To achieve particularly small transistor structures with high cutoff frequencies, after the diffusion of the collector region (4), the impurities of the base region (3) and those of the emitter region (1) are introduced into the surface of the collector region (4) by masked ion implantation, and the implanted ions are then activated in a single tempering process, during which the base region (3) and the emitter region (1) are formed below a protective insulating layer (5) which remains on the semiconductor surface. In the protective insulating layer, windows are formed for depositing the contacts (6, 7, 8) of the collector region (4), the base region (3), and the emitter region (1).

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patent: 3928081 (1975-12-01), Marley et al.
patent: 4018627 (1977-04-01), Polata
patent: 4106954 (1978-08-01), Brebisson et al.
patent: 4133704 (1979-01-01), MacIver et al.
Briska et al., IBM-TDB, 23 (1980), 644.

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