Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making named article
Reexamination Certificate
2000-10-12
2003-01-21
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making named article
C430S320000, C430S322000, C430S324000, C430S313000, C430S317000, C430S330000, C438S031000, C438S032000, C438S029000, C438S044000, C385S014000, C385S131000
Reexamination Certificate
active
06509139
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method of fabricating an integrated optical component on a silicon-on-insulator (SOI) chip comprising a layer of silicon separated from a substrate by an insulating layer, the component having a first set of features at a first level in the silicon layer and a second set of features at a second level in the silicon layer. The invention also relates to an optical component obtainable by the method.
BACKGROUND ART
Integrated optical components may be fabricated in the silicon layer of an SOI chip. The silicon layer is typically up to 5 microns thick (but, in some cases, may be up to 10 microns thick) and features are defined therein by photolithographic techniques. Such optical components need to be fabricated with a high degree of accuracy to enable them to function correctly and known fabrication methods produce satisfactory yields for components formed on such chips.
In some cases, however, e.g. where a low loss optical connection is required between an integrated optical component and an optical fibre, there is a need to increase the thickness of the silicon layer, e.g. up to 13 microns or higher. If the SOI chip is initially fabricated with a silicon-layer of lower thickness, the thickness of the layer can be increased e.g. by epitaxial growth. Problems are, however, encountered in fabricating optical components in such thick silicon layers with sufficient accuracy, particularly when two stages of photolithography are required to form features at two different levels in the silicon layer. There are two principal reasons for the problem. Firstly, the thickness of the silicon layer of an SOI chip is not uniform and the thicker the layer, the greater the variations. Secondly, the accuracy with which a feature, particularly a depth dimension, can be etched, decreases with the thickness of the silicon layer, i.e. the deeper the etch the greater the variation in its dimensions. These two sources of inaccuracy tend to be accumulative. The problems become worse as the depth of the silicon layer and hence the depth of the features to be fabricated therein increase. This results in a gradual reduction in yield as thicker silicon layers are used and it has been found that the yield may fall to an unacceptably low level for components fabricated in a silicon layer having a thickness of 10 microns or more.
The invention aims to provide an improved method of fabricating integrated optical components which increases the yield in such circumstances.
DISCLOSURE OF INVENTION
According to a first aspect of the invention there is provided a method of fabricating an integrated optical component on a silicon-on-insulator chip comprising a silicon layer separated from a substrate by an insulating layer, the component having a first set of features at a first level in the silicon layer adjacent the insulating layer and a second set of features at a second level in the silicon layer further from the insulating layer, the method comprising the steps of:
selecting a silicon-on-insulator chip having a silicon layer of sufficient thickness for the first set of features;
fabricating the first set of features in the silicon layer so as to form said first set of features at a first level in the silicon layer;
increasing the thickness of the silicon layer in selected areas so as to form a second level of the silicon layer over at least part of the first level; and
fabricating the second set of features at the second level in the silicon layer.
Accordingly to a further aspect of the invention there is provided an integrated optical component obtainable by such a method.
According to another aspect of the invention there is provided an integrated optical component on a silicon-on-insulator chip comprising a silicon layer separated from a substrate by an insulating layer comprising a first set of features at a first level in the silicon layer adjacent the insulating layer and a second set of features at a second level in the silicon layer further from the insulating layer, wherein the thickness of the silicon layer is 10 microns or more and the depth dimensions of the first set of features are formed to an accuracy of ±1.5%.
According to yet another aspect of the invention there is provided an integrated optical component on a silicon-on-insulator chip comprising a silicon layer separated from a substrate by an insulating layer, the component comprising a rib waveguide formed in the silicon layer so as to overhang an inclined end face of a V-groove formed in the chip, the end of the waveguide comprising a tapered structure in the form of a triangular shaped portion on top of the rib waveguide and comprising a widened portion in the form of a T-bar at the wide end of said tapered structure.
Preferred and optional features will be apparent from the following descriptions and from the subsidiary claims of the specification.
REFERENCES:
patent: 5841931 (1998-11-01), Foresi et al.
patent: 6316281 (2001-11-01), Lee et al.
patent: 2345980 (2001-08-01), None
Drake John Paul
Harpin Arnold Peter Roscoe
Roberts Stephen William
Bookham Technology PLC
Chacko-Davis Daborah
Fleshner & Kim LLP
Huff Mark F.
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